SCPS126G September   2006  – March 2021 PCA9538

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 RESET Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
      1. 7.2.1 RESET Input
        1. 7.2.1.1 RESET Errata
          1.        System Impact
          2.        System Workaround
      2. 7.2.2 Power-On Reset
      3. 7.2.3 I/O Port
      4. 7.2.4 Interrupt Output ( INT)
        1. 7.2.4.1 Interrupt Errata
          1.        System Impact
          2.        System Workaround
    3. 7.3 Programming
      1. 7.3.1 I2C Interface
    4. 7.4 Register Maps
      1. 7.4.1 Device Address
      2. 7.4.2 Control Register And Command Byte
      3. 7.4.3 Register Descriptions
      4. 7.4.4 Bus Transactions
        1. 7.4.4.1 Writes
        2. 7.4.4.2 Reads
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information Disclaimer
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Minimizing ICC When I/Os Control Leds
  9. 9 Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Power-On Reset Requirements

In the event of a glitch or data corruption, PCA9538 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 9-1 and Figure 9-2.

GUID-9C69E0F5-EA7B-489D-ACEC-BE801281EC5D-low.gifFigure 9-1 VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
GUID-E7AE7CD3-86D2-4DA9-AF3F-FE27B8571D67-low.gifFigure 9-2 VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC

Table 9-1 specifies the performance of the power-on reset feature for PCA9538 for both types of power-on reset.

Table 9-1 Recommended Supply Sequencing And Ramp Rates(1)
PARAMETERMINTYPMAXUNIT
VCC_FTFall rateSee Figure 9-11100ms
VCC_RTRise rateSee Figure 9-10.01100ms
VCC_TRR_GNDTime to re-ramp (when VCC drops to GND)See Figure 9-10.001ms
VCC_TRR_POR50Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)See Figure 9-20.001ms
VCC_GHLevel that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μsSee Figure 9-31.2V
VCC_GWGlitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCxSee Figure 9-3μs
VPORFVoltage trip point of POR on falling VCC0.7671.144V
VPORRVoltage trip point of POR on rising VCC1.0331.428V
(1) TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and the device impedance are factors that affect power-on reset performance. Figure 9-3 and Table 9-1 provide more information on how to measure these specifications.

GUID-21907428-460E-4DF3-ABFB-4B543E3BE922-low.gifFigure 9-3 Glitch Width And Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-4 and Table 9-1 provide more details on this specification.

GUID-BB5C9265-29A6-464F-AE12-6466FC1F82EF-low.gifFigure 9-4 VPOR