SCPS148I October   2005  – June 2022 PCA9546A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Interrupt and Reset Timing Requirements
    8. 6.8 Switching Characteristics
  7. 7 Parameter Measurement Information
    1.     16
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
        1. 8.4.1.1 RESET Errata
          1.        24
          2.        25
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Control Register
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register Description
      3. 8.6.3 Control Register Definition
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN MAX UNIT
I2C BUS—STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 µs
tscl I2C clock low time 4.7 µs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0(1) ns
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 300 ns
tbuf I2C bus free time between stop and start 4.7 µs
tsts I2C start or repeated start condition setup 4.7 µs
tsth I2C start or repeated start condition hold 4 µs
tsps I2C stop condition setup 4 µs
tvdL(Data) Valid data time (high to low)(2) SCL low to SDA output low valid 1 µs
tvdH(Data) Valid data time (low to high)(2) SCL low to SDA output high valid 0.6 µs
tvd(ack) Valid data time of ACK condition ACK signal from SCL low to
SDA (out) low		 1 µs
Cb I2C bus capacitive load 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-1)
MIN MAX UNIT
I2C BUS—FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 µs
tscl I2C clock low time 1.3 µs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0(1) ns
ticr I2C input rise time 20 + 0.1Cb (2) 300 ns
ticf I2C input fall time 20 + 0.1Cb (2) 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 20 + 0.1Cb (2) 300 ns
tbuf I2C bus free time between stop and start 1.3 µs
tsts I2C start or repeated start condition setup 0.6 µs
tsth I2C start or repeated start condition hold 0.6 µs
tsps I2C stop condition setup 0.6 µs
tvdL(Data) Valid data time (high to low)(3) SCL low to SDA output low valid 1 µs
tvdH(Data) Valid data time (low to high)(3) SCL low to SDA output high valid 0.6
tvd(ack) Valid data time of ACK condition ACK signal from SCL low to
SDA (out) low		 1 µs
Cb I2C bus capacitive load 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-1)