SCPS133K
December 2005 – December 2024
PCA9557
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
I2C Interface Timing Requirements
5.7
Reset Timing Requirements
5.8
Switching Characteristics
5.9
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Functional Block Diagram
7.2
Feature Description
7.2.1
RESET
7.2.1.1
RESET Errata
7.2.1.1.1
System Impact
7.2.1.1.2
System Workaround
7.2.2
Power-On Reset
7.3
Programming
7.3.1
I2C Interface
7.4
Register Maps
7.4.1
Device Address
7.4.2
Control Register And Command Byte
7.4.3
Register Descriptions
7.4.3.1
Bus Transactions
7.4.3.1.1
Writes
7.4.3.1.2
Reads
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Detailed Design Procedure
8.2.1.1
Minimizing ICC when I/O is Used to Control LED
8.3
Power Supply Recommendations
8.3.1
Power-On Reset Errata
8.3.1.1
System Impact
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGV|16
MPDS006C
PW|16
MPDS361A
DB|16
MPDS507A
RGY|16
MPQF115G
D|16
MPDS178G
RGV|16
MPQF121F
Thermal pad, mechanical data (Package|Pins)
RGY|16
QFND040P
RGV|16
QFND107G
Orderable Information
scps133k_oa
scps133k_pm
1
Features
Low standby current consumption of 1μA maximum
I
2
C to parallel port expander
Operating power-supply voltage range of 2.3V to 5.5V
5V Tolerant I/O ports
400kHz Fast I
2
C bus
Three hardware address pins allow for use of up to eight devices on I
2
C/SMBus
Lower-voltage higher-performance migration path for PCA9556
Input and output configuration register
Polarity inversion register
Active-low reset input
Internal power-on reset
High-impedance open drain on P0
Power up with all channels configured as inputs
No glitch on power up
Noise filter on SCL or SDA inputs
Latched outputs with high current drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100mA per JESD 78, class II
ESD protection exceeds JESD 22
2000V Human-body model (A114-A)
200V Machine model (A115-A)
1000V Charged-device model (C101)