8.3.1 System Clock and Reset Functions

8.3.1.1 System Clock Input

The PCM175x-Q1 family of devices requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 lists examples of system clock frequencies for common audio sampling rates.

Figure 20 shows and the System Clock Input Timing table lists the timing requirements for the system clock input. For optimal performance, use a clock source with low phase-jitter and noise. TI's PLL170x family of multiclock generators is an excellent choice for providing the PCM175x-Q1 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY	SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
	128 fS	192 fS	256 fS	384 fS	512 fS	768 fS	1152 fS
8 kHz	1.024	1.536	2.048	3.072	4.096	6.144	9.216
16 kHz	2.048	3.072	4.096	6.144	8.192	12.288	18.432
32 kHz	4.096	6.144	8.192	12.288	16.384	24.576	36.864
44.1 kHz	5.6448	8.4672	11.2896	16.9344	22.5792	33.8688	See (1)
48 kHz	6.144	9.216	12.288	18.432	24.576	36.864	See (1)
88.2 kHz	11.2896	16.9344	22.5792	33.8688	45.1584	See (1)	See (1)
96 kHz	12.288	18.432	24.576	36.864	49.152	See (1)	See (1)
192 kHz	24.576	36.864	See (1)	See (1)	See (1)	See (1)	See (1)

(1) This system clock rate is not supported for the given sampling frequency.

For timing specifications, see the System Clock Input Timing table.

Figure 20. System Clock Input Timing

8.3.1.2 Power-On Reset Functions

The PCM175x-Q1 family of devices includes a power-on reset function. Figure 21 shows the operation of this function. With the system clock active and V_CC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V_CC > 3 V (typical, 2.2 V to
3.7 V).

During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or V_CC / 2. After the reset period, an internal register is initialized in the next 1 / f_S period and if SCK, BCK, and LRCK are provided continuously, the PCM175x-Q1 family of devices provides proper analog output with unit group delay against the input data.

Figure 21. Power-On Reset Timing

8.3.2 Audio Serial Interface

The audio serial interface for the PCM175x-Q1 family of devices consists of a 3-wire synchronous serial port. The interface includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). The BCK pin is the serial audio bit clock, and is used to clock the serial data present on the DATA pin into the serial shift register of the audio interface. Serial data is clocked into the PCM175x-Q1 family of devices on the rising edge of BCK. The LRCK pin is the serial audio left and right word clock. This pin is used to latch serial data into the internal registers of the serial audio interface.

Both the LRCK and BCK pins should be synchronous to the system clock. Ideally, TI recommends that the LRCK and BCK pins be derived from the system clock input, SCK. The LRCK pin is operated at the sampling frequency, f_S. The BCK pin can operate at 32, 48, or 64 times the sampling frequency for standard (right-justified) format, and 32 times the sampling frequency of the BCK pin is limited to 16-bit right-justified format only. The BCK pin can operate at 48 or 64 times the sampling frequency for the I²S and left-justified formats, and 48 times the sampling frequency of the BCK pin is limited to 192, 384, and 768 f_S SCKI.

Internal operation of the PCM175x-Q1 family of devices is synchronized with the LRCK pin. Accordingly, internal operation is held when the sampling rate clock of the LRCK pin changes or when the SCK pin, BCK pin, or both pins are interrupted for a 3-bit clock cycle or longer. If the SCK, BCK, and LRCK pins are provided continuously after this held condition, the internal operation is re-synchronized automatically in a period of less than 3 / f_S. External resetting is not required.

8.3.2.1 Audio Data Formats and Timing

The PCM1753-Q1 device supports industry-standard audio data formats, including right-justified, I²S, and left-justified. The PCM1754-Q1 device supports I²S and 16-bit-word right-justified audio data formats. Figure 23 shows the data formats. Data formats are selected using the format bits, FMT[2:0], located in control register 20 of the PCM1753-Q1 device, and are selected using the FMT pin on the PCM1754-Q1 device. The default data format is 24-bit left-justified. All formats require binary 2s-complement MSB-first audio data. Figure 22 shows a detailed timing diagram for the serial audio interface. The Audio Interface Timing table lists the audio interface timing requirements.

For timing specifications, see the Audio Interface Timing table.

Figure 22. Audio Interface Timing

Figure 23. Audio Data Input Formats

8.3.3 Zero Flag (PCM1754-Q1)

The PCM1754-Q1 device has a ZERO flag pin, ZEROA (pin 11). The ZEROA pin is the L-channel and R-channel common zero flag pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clock periods), the ZEROA pin is set to a logic 1 state.

8.3.4 Zero Flag (PCM1753-Q1)

Zero-Detect Condition

Zero detection for either output channel is independent from the other channel. If the data for a given channel remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.

8.3.5 Zero Flag Outputs

If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic 1 state. Each channel has zero flag pins, ZEROL (pin 12) and ZEROR (pin 11). These pins can operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally controlled function. The active polarity of the zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The reset default is active-high output, or ZREV set to 0. The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22 to 1. The reset default is independent zero flags for L-channel and R-channel, or AZRO set to 0.

8.3.6 Analog Outputs

The PCM1753-Q1 device includes two independent output channels, V_OUTL and V_OUTR. These are unbalanced outputs, each capable of driving 4 V_PP typical into a 5-kΩ ac-coupled load. The internal output amplifiers for V_OUTL and V_OUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 V_CC.

The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise shaping characteristics of the PCM1754-Q1 delta-sigma DAC. The frequency response of this filter is shown in Figure 24. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications Information section of this data sheet.

Figure 24. Level vs Frequency
Output Filter Frequency Response

8.3.6.1 V_COM Output

One unbuffered common-mode voltage output pin, V_COM (pin 10) is brought out for decoupling purposes. This pin is nominally biased to a DC-voltage level that is equal to 0.5 V_CC. This pin can be used to bias external circuits. Figure 25 shows an example of using the V_COM pin for external biasing applications.

Figure 25. Biasing External Circuits Using the V_COM Pin

8.4.1 Hardware Control (PCM1754-Q1)

The digital functions of the PCM1754-Q1 device are capable of hardware control. Table 2 lists selectable formats, Table 3 lists de-emphasis control, and Table 4 lists mute control.

8.4.2 Oversampling Rate Control (PCM1754-Q1)

The PCM1754-Q1 device automatically controls the oversampling rate of the delta-sigma DACs with the system clock rate. The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.

8.5.1 Software Control (PCM1753-Q1)

The PCM1753-Q1 device has many programmable functions which can be controlled in the software control mode. The functions are controlled by programming the internal registers using ML, MC, and MD.

The serial control interface is a 3-wire serial port, which operates asynchronously to the audio serial interface. The serial control interface is used to program the on-chip mode registers. The control interface includes the MD (pin 13), MC (pin 14), and ML (pin 15) pins. The MD pin is the serial data input, used to program the mode registers. The MC pin is the serial bit clock, used to shift data into the control port. The ML pin is the control port latch clock.

8.5.1.1 Register Write Operation

All write operations for the serial control port use 16-bit data words. Figure 26 shows the control data word format. The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].

Figure 27 shows the functional timing diagram for writing to the serial control port. ML is held at a logic 1 state until a register needs to be written. To begin the register write cycle, ML is set to logic 0. Sixteen clocks are then provided on the MC pin, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has completed, ML is set to logic 1 to latch the data into the indexed mode control register.

Figure 26. Control Data Word Format for MD

Figure 27. Register Write Operation

8.6.1 Mode Control Registers (PCM1753-Q1)

8.6.1.2 Register Definitions

8.6.1.2.1 ATx[7:0]: Digital Attenuation Level Setting

With x = 1 or 2, corresponding to the DAC output V_OUTL (x = 1) and V_OUTR (x = 2).

Default value: 1111 1111b

Each DAC channel (V_OUTL and V_OUTR) includes a digital attenuation function. The attenuation level can be set from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuator levels are made by incrementing or decrementing one step (0.5 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute).

The attenuation data for each channel can be set individually. The attenuation level is set using Equation 1.

Equation 1. Attenuation level (dB) = 0.5 × (ATx[7:0]_DEC – 255)

where

• ATx[7:0]_DEC = 0 through 255.

For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation.

The table in Figure 28 shows the attenuation levels for various settings.

Figure 28. Attenuation Level Settings

8.6.1.2.2 MUTx: Soft Mute Control

With x = 1 or 2, corresponding to the DAC outputs V_OUTL (x = 1) and V_OUTR (x = 2).

Default value: 0

The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (0.5 dB) for every 8 / f_S seconds. This provides pop-free muting of the DAC output.

By setting MUTx = 0, the attenuator is increased one step for every 8/f_S seconds to the previously programmed attenuation level.

8.6.1.2.3 OVER: Oversampling Rate Control

Default value: 0

System clock rate = 256 f_S, 384 f_S, 512 f_S, 768 f_S, or 1152 f_S:

System clock rate = 128 f_S or 192 f_S:

The OVER bit is used to control the oversampling rate of the delta-sigma DAC. The OVER = 1 setting is recommended when the sampling rate is 192 kHz (system clock rate is 128 f_S or 192 f_S).

8.6.1.2.4 SRST: Reset

Default value: 0

The SRST bit is used to enable or disable the soft reset function. The operation is the same as power-on reset. All registers are initialized.

8.6.1.2.5 DACx: DAC Operation Control

With x = 1 or 2, corresponding to the DAC output V_OUTL (x = 1) or V_OUTR (x = 2).

Default value: 0

The DAC operation controls are used to enable and disable the DAC outputs, V_OUTL and V_OUTR. When DACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When DACx = 1, the corresponding output is set to the bipolar zero level, or 0.5 V_CC.

8.6.1.2.6 DM12: Digital De-Emphasis Function Control

Default value: 0

The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical Characteristics section of this data sheet.

8.6.1.2.7 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function

Default value: 00

The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled.

8.6.1.2.8 FMT[2:0]: Audio Interface Data Format

Default value: 101

The FMT[2:0] bits are used to select the data format for the serial audio interface. The table in Figure 29 shows the available format options.

Figure 29. Audio Data Format Options

8.6.1.2.9 FLT: Digital Filter Rolloff Control

Default value: 0

The FLT bit allows the user to select the digital filter rolloff that is best suited to the application. Two filter rolloff selections are available, sharp and slow. The filter responses for these selections are shown in the Typical Characteristics section of this data sheet.

8.6.1.2.10 DREV: Output Phase Select

Default value: 0

The DREV bit is the output analog signal phase control.

8.6.1.2.11 ZREV: Zero Flag Polarity Select

Default value: 01h

The ZREV bit allows the user to select the polarity of zero flag pins.

8.6.1.2.12 AZRO: Zero Flag Function Select

Default value: 0

The AZRO bit allows the user to select the function of zero flag pins.