SLES092E April   2003  – July 2019 PCM1753 , PCM1754 , PCM1755

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Clock Input Timing
    7. 7.7 Audio Interface Timing
    8. 7.8 Control Interface Timing Requirements
    9. 7.9 Typical Characteristics
      1. 7.9.1 Digital Filter (De-Emphasis Off)
      2. 7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)
      3. 7.9.3 Analog Dynamic Performance (Temperature Characteristics)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 System Clock and Reset Functions
        1. 8.3.1.1 System Clock Input
        2. 8.3.1.2 Power-On Reset Functions
      2. 8.3.2 Audio Serial Interface
        1. 8.3.2.1 Audio Data Formats and Timing
      3. 8.3.3 Zero Flag (PCM1754)
      4. 8.3.4 Zero Flag (PCM1753)
      5. 8.3.5 Zero Flag Outputs
      6. 8.3.6 Analog Outputs
        1. 8.3.6.1 VCOM Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control (PCM1754)
      2. 8.4.2 Oversampling Rate Control (PCM1754)
    5. 8.5 Programming
      1. 8.5.1 Software Control (PCM1753/55)
        1. 8.5.1.1 Register Write Operation
    6. 8.6 Register Maps
      1. 8.6.1 Mode Control Registers (PCM1753/55)
        1. 8.6.1.1 User-Programmable Mode Controls
        2. 8.6.1.2 Register Definitions
          1. 8.6.1.2.1  ATx[7:0]: Digital Attenuation Level Setting
          2. 8.6.1.2.2  MUTx: Soft Mute Control
          3. 8.6.1.2.3  OVER: Oversampling Rate Control
          4. 8.6.1.2.4  SRST: Reset
          5. 8.6.1.2.5  DACx: DAC Operation Control
          6. 8.6.1.2.6  DM12: Digital De-Emphasis Function Control
          7. 8.6.1.2.7  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          8. 8.6.1.2.8  FMT[2:0]: Audio Interface Data Format
          9. 8.6.1.2.9  FLT: Digital Filter Rolloff Control
          10. 8.6.1.2.10 DREV: Output Phase Select
          11. 8.6.1.2.11 ZREV: Zero Flag Polarity Select
          12. 8.6.1.2.12 AZRO: Zero Flag Function Select
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Design Parameters
        2. 9.2.1.2 Power Supplies and Grounding
        3. 9.2.1.3 D/A Output Filter Circuits
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Total Harmonic Distortion + Noise
        2. 9.2.2.2 Dynamic Range
        3. 9.2.2.3 Idle Channel Signal-to-Noise Ratio (SNR)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
fS Sampling frequency 5 200 kHz
System clock frequency 128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152 fS 		kHz
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
VIH Input logic level, high 2 VDC
VIL Input logic level, low 0.8 VDC
IIH Input logic current, high (SCK, BCK, DATA, and LRCK pins) VIN = VCC 10 µA
IIL Input logic current, low (SCK, BCK, DATA, and LRCK pins) VIN = 0 V -10 µA
IIH Input logic current, high (TEST, DEMP, MUTE, and FMT pins) VIN = VCC 65 100 µA
IIL Input logic current, low (TEST, DEMP, MUTE, and FMT pins) VIN = 0 V -10 µA
VOH Output logic level, high (ZEROA pin) IOH = –1 mA 2.4 VDC
VOL Output logic level, low (ZEROA pin) IOL = 1 mA 0.4 VDC
DYNAMIC PERFORMANCE(1)(2)
THD+N at VOUT = 0 dB fS = 44.1 kHz 0% 0.01%
fS = 96 kHz 0%
fS = 192 kHz 0%
THD+N at VOUT = -60 dB fS = 44.1 kHz 0.65%
fS = 96 kHz 0.80%
fS = 192 kHz 0.95%
Dynamic range EIAJ, A-weighted, fS = 44.1 kHz 100 106 dB
A-weighted, fS = 96 kHz 104
A-weighted, fS = 192 kHz 102
Signal-to-noise ratio EIAJ, A-weighted, fS = 44.1 kHz 100 106 dB
A-weighted, fS = 96 kHz 104
A-weighted, fS = 192 kHz 102
Channel separation fS = 44.1 kHz 97 103 dB
fS = 96 kHz 101
fS = 192 kHz 100
Level linearity error VOUT = -90 dB ±0.5 dB
DC ACCURACY
Gain error ±1 ±6 % of FSR
Gain mismatch, channel-to-channel ±1 ±3 % of FSR
Bipolar zero error VOUT = 0.5 VCC at BPZ ±30 ±60 mV
ANALOG OUTPUT
Output voltage Full scale (0 dB) 80% of VCC VPP
Center voltage 50% of VCC VDC
Load impedance AC-coupled load 5 kΩ
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS (SHARP ROLLOFF)
Pass band ±0.04 dB 0.454 fS
Stop band 0.546 fs
Pass-band ripple ±0.04 dB
Stop-band attenuation Stop band = 0.546 fS –50 dB
ANALOG FILTER PERFORMANCE
Frequency response At 20 kHz –0.03 dB
At 44 kHz –0.2
POWER SUPPLY REQUIREMENTS(2)
ICC Supply current fS = 44.1 kHz 16 21 mA
fS = 96 kHz 25
fS = 192 kHz 30
Power dissipation fS = 44.1 kHz 80 105 mW
fS = 96 kHz 125
fS = 192 kHz 150
TEMPERATURE
RθJA Thermal Resistance 16-pin DBQ 104.1 °C/W
(1) Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in the averaging mode.
(2) Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18.