SBAS451B October   2008  – August  2015 PCM1789

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Digital Input/Output
    6. 6.6  Electrical Characteristics: DAC
    7. 6.7  Electrical Characteristics: Power-Supply Requirements
    8. 6.8  System Clock Timing Requirements
    9. 6.9  Audio Interface Timing Requirements
    10. 6.10 Three-Wire Timing Requirements
    11. 6.11 SCL and SDA Timing Requirements
    12. 6.12 Typical Characteristics
      1. 6.12.1 Digital Filter
      2. 6.12.2 Digital De-Emphasis Filter
      3. 6.12.3 Dynamic Performance
      4. 6.12.4 Output Spectrum
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Outputs
      2. 7.3.2  Voltage Reference VCOM
      3. 7.3.3  System Clock Input
      4. 7.3.4  Reset Operation
      5. 7.3.5  ZERO Flag
      6. 7.3.6  AMUTE Control
      7. 7.3.7  Three-Wire (SPI) Serial Control
      8. 7.3.8  Control Data Word Format
      9. 7.3.9  Register Write Operation
      10. 7.3.10 Timing Requirements
      11. 7.3.11 Two-wire (I2C) Serial Control
      12. 7.3.12 Packet Protocol
      13. 7.3.13 Write Operation
      14. 7.3.14 Read Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sampling Mode
      2. 7.4.2 Audio Serial Port Operation
      3. 7.4.3 Audio Data Interface Formats and Timing
      4. 7.4.4 Audio Interface Timing
      5. 7.4.5 Synchronization with the Digital Audio System
      6. 7.4.6 MODE Control
      7. 7.4.7 Parallel Hardware Control
    5. 7.5 Register Maps
      1. 7.5.1 Control Register Definitions (Software Mode Only)
      2. 7.5.2 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Connection Diagrams
      2. 8.1.2 Power Supply and Grounding
      3. 8.1.3 Low-Pass Filter and Differential-to-Single-Ended Converter For DAC Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware Control Method
        2. 8.2.2.2 Audio Input
        3. 8.2.2.3 Audio Output
        4. 8.2.2.4 Master Clock
    3. 8.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
PCM1789 po_bas451.gif

Pin Functions

PIN I/O PULL-DOWN 5-V TOLERANT DESCRIPTION
NAME NO.
LRCK 1 I Yes No Audio data word clock input
BCK 2 I Yes No Audio data bit clock input
DIN 3 I No No Audio data input
RST 4 I Yes Yes Reset and power-down control input with active low
SCKI 5 I No Yes System clock input
VDD 6 — — — Digital power supply, +3.3 V
DGND 7 — — — Digital ground
VCC1 8 — — — Analog power supply 1, +5 V
VCOM 9 — — — Voltage common decoupling
AGND1 10 — — — Analog ground 1
VOUTL– 11 O No No Negative analog output from DAC left channel
VOUTL+ 12 O No No Positive analog output from DAC left channel
VOUTR+ 13 O No No Positive analog output from DAC right channel
VOUTR– 14 O No No Negative analog output from DAC right channel
AGND2 15 — — — Analog ground 2
VCC2 16 — — — Analog power supply 2, +5 V
AMUTEI 17 I No Yes Analog mute control input with active low
ZERO2/AMUTEO 18 O No No Zero detect flag output 2/Analog mute control output(1) with active low
ZERO1 19 O No No Zero detect flag output 1
MODE 20 I No No Control port mode selection. Tied to VDD: SPI, ADR6 = 1, pull-up: SPI, ADR6 = 0, pull-down: H/W auto mode, tied to DGND: I2C
MD/SDA/DEMP 21 I/O No Yes Input data for SPI, data for I2C(1), de-emphasis control for hardware control mode
MC/SCL/FMT 22 I No Yes Clock for SPI, clock for I2C, format select for hardware control mode
MS/ADR0/RSV 23 I Yes Yes Chip Select for SPI, address select 0 for I2C, reserve (set low) for hardware control mode
ADR5/ADR1/RSV 24 I No Yes Address select 5 for SPI, address select 1 for I2C, reserve (set low) for hardware control mode
(1) Open-drain configuration in out mode.