SBAS451B October   2008  – August  2015 PCM1789

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Digital Input/Output
    6. 6.6  Electrical Characteristics: DAC
    7. 6.7  Electrical Characteristics: Power-Supply Requirements
    8. 6.8  System Clock Timing Requirements
    9. 6.9  Audio Interface Timing Requirements
    10. 6.10 Three-Wire Timing Requirements
    11. 6.11 SCL and SDA Timing Requirements
    12. 6.12 Typical Characteristics
      1. 6.12.1 Digital Filter
      2. 6.12.2 Digital De-Emphasis Filter
      3. 6.12.3 Dynamic Performance
      4. 6.12.4 Output Spectrum
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Outputs
      2. 7.3.2  Voltage Reference VCOM
      3. 7.3.3  System Clock Input
      4. 7.3.4  Reset Operation
      5. 7.3.5  ZERO Flag
      6. 7.3.6  AMUTE Control
      7. 7.3.7  Three-Wire (SPI) Serial Control
      8. 7.3.8  Control Data Word Format
      9. 7.3.9  Register Write Operation
      10. 7.3.10 Timing Requirements
      11. 7.3.11 Two-wire (I2C) Serial Control
      12. 7.3.12 Packet Protocol
      13. 7.3.13 Write Operation
      14. 7.3.14 Read Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sampling Mode
      2. 7.4.2 Audio Serial Port Operation
      3. 7.4.3 Audio Data Interface Formats and Timing
      4. 7.4.4 Audio Interface Timing
      5. 7.4.5 Synchronization with the Digital Audio System
      6. 7.4.6 MODE Control
      7. 7.4.7 Parallel Hardware Control
    5. 7.5 Register Maps
      1. 7.5.1 Control Register Definitions (Software Mode Only)
      2. 7.5.2 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Connection Diagrams
      2. 8.1.2 Power Supply and Grounding
      3. 8.1.3 Low-Pass Filter and Differential-to-Single-Ended Converter For DAC Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware Control Method
        2. 8.2.2.2 Audio Input
        3. 8.2.2.3 Audio Output
        4. 8.2.2.4 Master Clock
    3. 8.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VCC1, VCC2 –0.3 6.5 V
VDD –0.3 4.0
Ground voltage differences AGND1, AGND2, DGND ±0.1 V
Supply voltage differences VCC1, VCC2 0.1 V
Digital input voltage RST, ADR5, MS, MC, MD, SCKI, AMUTEI –0.3 6.5 V
BCK, LRCK, DIN, MODE, ZERO1, ZERO2 –0.3 (VDD + 0.3) < +4.0
Analog input voltage VCOM, VOUTL±, VOUTR± –0.3 (VCC + 0.3) < +6.5 V
Input current (all pins except supplies) ±10 mA
Ambient temperature under bias –40 125 °C
Junction temperature 150 °C
Package temperature (IR reflow, peak) 260 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Analog supply voltage, VCC 4.5 5.0 5.5 V
Digital supply voltage, VDD 3.0 3.3 3.6 V
Digital Interface LVTTL-compatible
Digital input clock frequency Sampling frequency, LRCK 8 192 kHz
System clock frequency, SCKI 2.048 36.864 MHz
Analog output voltage Differential 8 VPP
Analog output load resistance To ac-coupled GND 5 kΩ
To dc-coupled GND 15
Analog output load capacitance 50 pF
Digital output load capacitance 20 pF
Operating free-air temperature PCM1789 consumer grade –40 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) PCM1789 UNIT
PW (TSSOP)
24 PINS
RθJA Junction-to-ambient thermal resistance 87.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.3 °C/W
RθJB Junction-to-board thermal resistance 42.6 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 42.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: Digital Input/Output

All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA FORMAT
fS Sampling frequency 8 48 192 kHz
System clock frequency 128 fS, 192 fS, 256 fS,
384 fS, 512 fS, 768 fS, 1152 fS		 2.048 36.864 MHz
INPUT LOGIC
LOGIC FAMILY
VIH Input logic level, high (BCK, LRCK, and DIN) 2.0 VDD VDC
VIL Input logic level, low (BCK, LRCK, and DIN) 0.8 VDC
VIH Input logic current, high (SCKI, ADR5/ADR1/RSV, MC/SCL/FMT, MD/SDA?DEMP, and AMUTEI) 2.0 5.5 VDC
VIL Input logic current, low (SCKI, ADR5/ADR1/RSV, MC/SCL/FMT, MD/SDA/DEMP, and AMUTEI) 0.8 VDC
IIH Input logic current, high (DIN, SCKI, ADR5/ADR1/RSV, MC/SCL/FMT, MD/SDA/DEMP, and AMUTEI) VIN = VDD ±10 μA
IIL Input logic current, low (DIN, SCKI, ADR5/ADR1/RSV, MC/SCL/FMT, MD/SDA/DEMP, and AMUTEI) VIN = 0 V ±10 μA
IIH Input logic current, high (BCK, LRCK, RST, MS/ADR0/RSV) VIN = VDD +65 +100 μA
Input logic current, low (BCK, LRCK, RST, MS/ADR0/RSV) VIN = 0 V ±10 μA
OUTPUT LOGIC
VOH Output logic level, high (ZERO1 and ZERO2) IOUT = –4 mA 2.4 VDC
VOL Output logic level, high (ZERO1 and ZERO2) IOUT = +4 mA 0.4 VDC
REFERENCE OUTPUT
VCOM output voltage 0.5 × VCC1 V
VCOM output impedance 7.5 kΩ
Allowable VCOM output source/sink current 1 μA

6.6 Electrical Characteristics: DAC

All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 16 24 Bits
DC ACCURACY
Gain mismatch channel-to-channel x ±2.0 ±6.0 % of FSR
Gain error ±2.0 ±6.0 % of FSR
Bipolar zero error ±1.0 % of FSR
DYNAMIC PERFORMANCE(1)(2)
THD+N Total harmonic distortion + noise VOUT = 0 dB fS = 48 kHz –94 –88 dB
fS = 96 kHz –94 dB
fS = 192 kHz –94 dB
Dynamic range fS = 48 kHz, EIAJ, A-weighted 106 113 dB
fS = 96 kHz, EIAJ, A-weighted 113 dB
fS = 192 kHz, EIAJ, A-weighted 113 dB
SNR Signal-to-noise ratio fS = 48 kHz, EIAJ, A-weighted 106 113 dB
fS = 96 kHz, EIAJ, A-weighted 113 dB
fS = 192 kHz, EIAJ, A-weighted 113 dB
Channel separation fS = 48 kHz 103 109 dB
fS = 96 kHz 109 dB
fS = 192 kHz 108 dB
ANALOG OUTPUT
Output voltage Differential 1.6 × VCC1 VPP
Center voltage 0.5 × VCC1 V
Load impedance To ac-coupled GND(3) 5 kΩ
To dc-coupled GND(3) 15 kΩ
LPF frequency response f = 20 kHz –0.04 dB
f = 44 kHz –0.18 dB
DIGITAL FILTER PERFORMANCE WITH SHARP ROLL-OFF
Passband (single, dual) Except SCKI = 128 fS and 192 fS 0.454 × fS Hz
SCKI = 128 fS and 192 fS 0.432 × fS Hz
Passband (quad) 0.432 × fS Hz
Stop band (single, dual) Except SCKI = 128 fS and 192 fS 0.546 × fS Hz
SCKI = 128 fS and 192 fS 0.569 × fS Hz
Stop band (quad) 0.569 × fS Hz
Passband ripple < 0.454 × fS, 0.432 × fS ±0.0018 dB
Stop band attenuation > 0.546 × fS, 0.569 × fS –75 dB
DIGITAL FILTER PERFORMANCE WITH SLOW ROLL-OFF
Passband 0.328 × fS Hz
Stop band 0.673 × fS Hz
Passband ripple < 0.328 × fS ±0.0013 dB
Stop band attenuation > 0.673 × fS –75 dB
DIGITAL FILTER PERFORMANCE
Group delay time (single, dual) Except SCKI = 128 fS and 192 fS 28/fS sec
SCKI = 128 fS and 192 fS 19/fS sec
Group delay time (quad) 19/fS sec
De-emphasis error ±0.1 dB
(1) In differential mode at VOUTx± pin, fOUT = 1 kHz, using Audio Precision System II, Average mode with 20-kHz LPF and 400-Hz HPF.
(2) fS = 48 kHz: SCKI = 512 fS (single), fS = 96 kHz : SCKI = 256 fS (dual), fS = 192 kHz : SCKI = 128 fS (quad).
(3) Allowable minimum input resistance of differential-to-single-ended converter with D-to-S gain = G is calculated as (1 + 2G)/(1 + G) × 5k for ac-coupled, and (1+ 0.9G)/(1 + G) × 15k for dc-coupled connection; refer to Figure 37 and Figure 38.

6.7 Electrical Characteristics: Power-Supply Requirements

All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER-SUPPLY REQUIREMENTS
VCC1/2 Voltage range 4.5 5.0 5.5 VDC
VDD 3.0 3.3 3.6 VDC
ICC Supply current fS = 48 kHz 19 28 mA
fS = 192 kHz 19 mA
Full power-down(1) 170 μA
IDD fS = 48 kHz 18 30 mA
fS = 192 kHz 22 mA
Full power-down(1) 60 μA
Power dissipation fS = 48 kHz 154 239 mW
fS = 192 kHz 168 mW
Full power-down(1) 1.05 mW
TEMPERATURE RANGE
Operating temperature PCM1789 consumer grade –40 +85 °C
θJA Thermal resistance TSSOP-24 115 °C/W
(1) SCKI, BCK, and LRCK stopped.

6.8 System Clock Timing Requirements

(see Figure 19)
MIN NOM MAX UNIT
tSCY System clock cycle tiime 27 ns
tSCH Syst4em clock width high 10 ns
tSCL System clock width low 10 ns
— System clock duty cycle 40% 60%

6.9 Audio Interface Timing Requirements

(see Figure 35)
MIN NOM MAX UNIT
tBCY BCK cycle time 75 ns
tBCH BCK pulse width high 35 ns
tBCL BCK pulse width low 35 ns
tLRW LRCK pulse width high (LJ, RJ and I2S formats) 1/(2 × fS) 1/(2 × fS) s
LRCK pulse width high (DSP format) tBCY tBCY s
tLRS LRCK setup time to BCK rising edge 10 ns
tLRH LRCK hold time to BCK rising edge 10 ns
tDIS DIN setup time to BCK rising edge 10 ns
tDIH DIN hold time to BCK rising edge 10 ns

6.10 Three-Wire Timing Requirements

(See Figure 24)
MIN NOM MAX UNIT
tMCY MC pulse cycle time 100 ns
tMCL MC low-level time 40 ns
tMCH MC high-level time 40 ns
tHCH MS high-level time tMCY ns
tMSS MS falling edge to MC rising edge 30 ns
tMHS MS rising edge from MC rising edge for LSB 15 ns
tMDH MS hold time 15 ns
tMDS MD setup time 15 ns

6.11 SCL and SDA Timing Requirements

(See Figure 1)
STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
fSCL SCL clock frequency 100 400 kHz
tBUF Bus free time between STOP and START condition 4.7 1.3 μs
tLOW Low period of the SCL clock 4.7 1.3 μs
tHI High period of the SCL clock 4.0 0.6 μs
tS-SU Setup time for START/Repeated START condition 4.7 0.6 μs
tS-HD Hold time for START/Repeated START condition 4.0 0.6 μs
tD-SU Data setup time 250 100 ns
tD-HD Data hold time 0 3450 0 900 ns
tSCL-R Rise time of SCL signal 1000 20 + 0.1 CB 300 ns
tSCL-F Fall time of SCL signal 1000 20 + 0.1 CB 300 ns
tSDA-R Rise time of SDA signal 1000 20 + 0.1 CB 300 ns
tSDA-F Fall time of SDA signal 1000 20 + 0.1 CB 300 ns
tP-SU Setup time for STOP condition 4.0 0.6 μs
tGW Allowable glitch width N/A 50 ns
CB Capacitive load for SDA and SCL line 400 100 pF
VNH Noise margin at high level for each connected device(including hysteresis) 0.2 × VDD 0.2 × VDD V
VNL Noise margin at low level for each connected device (including hysteresis) 0.1 × VDD 0.1 × VDD V
VHYS Hysteresis of Schmitt trigger input N/A 0.05 × VDD V
PCM1789 ai_tim_scl_sda_bas451.gifFigure 1. SCL and SDA Control Interface Timing

6.12 Typical Characteristics

6.12.1 Digital Filter

All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PCM1789 tc_fresp_single_bas451.gif
Figure 2. Frequency Response (Single Rate)
PCM1789 tc_fresp_dual_bas451.gif
Figure 4. Frequency Response (Dual Rate)
PCM1789 tc_fresp_quad_bas451.gif
Figure 6. Frequency Response (Quad Rate)
PCM1789 tc_fresp_pass_single_bas451.gif
Figure 3. Frequency Response Passband (Single Rate)
PCM1789 tc_fresp_pass_dual_bas451.gif
Figure 5. Frequency Response Passband (Dual Rate)
PCM1789 tc_fresp_pass_quad_bas451.gif
Figure 7. Frequency Response Passband (Quad Rate)

6.12.2 Digital De-Emphasis Filter

All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PCM1789 tc_de_emp_48k_bas451.gif
fS = 48 kHz
Figure 8. De-emphasis Characteristic
PCM1789 tc_de_emp_32k_bas451.gif
fS = 32 kHz
Figure 10. De-emphasis Characteristic
PCM1789 tc_de_emp_44p1k_bas451.gif
fS = 44.1 kHz
Figure 9. De-emphasis Characteristic
PCM1789 tc_ana_filt_bas451.gif
Figure 11. Analog Filter Characteristic

6.12.3 Dynamic Performance

All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PCM1789 tc_thd-tmp_bas451.gif
Figure 12. Total Harmonic Distortion + Noise
vs Temperature
PCM1789 tc_thd-vs_bas451.gif
Figure 14. Total Harmonic Distortion + Noise
vs Supply Voltage
PCM1789 tc_range_snr-tmp_bas451.gif
Figure 13. Dynamic Range and Signal-to-Noise Ratio
vs Temperature
PCM1789 tc_range_snr-vs_bas451.gif
Figure 15. Dynamic Range and Signal-to-Noise Ratio
vs Supply Voltage

6.12.4 Output Spectrum

All specifications at TA = +25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit data, and Sampling mode = Auto, unless otherwise noted.
PCM1789 tc_out_spec_0db_bas451.gif
0 dB, N = 32768
Figure 16. Output Spectrum
PCM1789 tc_out_spec_bpz_bas451.gif
BPZ, N = 32768
Figure 18. Output Spectrum
PCM1789 tc_out_spec_60db_bas451.gif
–60 dB, N = 32768
Figure 17. Output Spectrum