SLES248A May   2009  – March 2015 PCM1795

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Digital Filter
      2. 6.7.2 Digital Filter: De-Emphasis Filter
      3. 6.7.3 Analog Dynamic Performance: Supply Voltage Characteristics
      4. 6.7.4 Analog Dynamic Performance: Temperature Characteristics
      5. 6.7.5 Analog FIR Filter performance in DSD Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Data Interface
        1. 7.3.1.1 Audio Serial Interface
        2. 7.3.1.2 PCM Audio Data Formats and Timing
        3. 7.3.1.3 External Digital Filter Interface and Timing
        4. 7.3.1.4 Direct Stream Digital (DSD) Format Interface and Timing
        5. 7.3.1.5 TDMCA Interface
        6. 7.3.1.6 Analog Output
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 System Clock and Reset Functions
        1. 7.5.1.1 System Clock Input
        2. 7.5.1.2 Power-On and External Reset Functions
      2. 7.5.2 Function Descriptions
        1. 7.5.2.1 Zero Detect
      3. 7.5.3 Serial Control Interface
        1. 7.5.3.1 SPI Interface
        2. 7.5.3.2 Register Read/Write Operation
      4. 7.5.4 I2C Interface
        1. 7.5.4.1 Slave Address
        2. 7.5.4.2 Packet Protocol
        3. 7.5.4.3 Write Register
        4. 7.5.4.4 Read Register
        5. 7.5.4.5 Noise Suppression
    6. 7.6 Register Maps
      1. 7.6.1 Mode Control Registers
        1. 7.6.1.1 User-Programmable Mode Controls
        2. 7.6.1.2 Register Map
        3. 7.6.1.3 Register Definitions
          1. 7.6.1.3.1  R/W: Read/Write Mode Select
          2. 7.6.1.3.2  ATx[7:0]: Digital Attenuation Level Setting
          3. 7.6.1.3.3  R/W: Read/Write Mode Select
          4. 7.6.1.3.4  ATLD: Attenuation Load Control
          5. 7.6.1.3.5  FMT[2:0]: Audio Interface Data Format
          6. 7.6.1.3.6  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          7. 7.6.1.3.7  DME: Digital De-Emphasis Control
          8. 7.6.1.3.8  MUTE: Soft Mute Control
          9. 7.6.1.3.9  R/W: Read/Write Mode Select
          10. 7.6.1.3.10 REV: Output Phase Reversal
          11. 7.6.1.3.11 ATS[1:0]: Attenuation Rate Select
          12. 7.6.1.3.12 OPE: DAC Operation Control
          13. 7.6.1.3.13 DFMS: Stereo DF Bypass Mode Select
          14. 7.6.1.3.14 FLT: Digital Filter Roll-Off Control
          15. 7.6.1.3.15 INZD: Infinite Zero Detect Mute Control
          16. 7.6.1.3.16 R/W: Read/Write Mode Select
          17. 7.6.1.3.17 SRST: System Reset Control
          18. 7.6.1.3.18 DSD: DSD Interface Mode Control
          19. 7.6.1.3.19 DFTH: Digital Filter Bypass (or Through Mode) Control
          20. 7.6.1.3.20 MONO: Monaural Mode Selection
          21. 7.6.1.3.21 CHSL: Channel Selection for Monaural Mode
          22. 7.6.1.3.22 OS[1:0]: ΔΣ Oversampling Rate Selection
          23. 7.6.1.3.23 R/W: Read/Write Mode Select
          24. 7.6.1.3.24 DZ[1:0]: DSD Zero Output Enable
          25. 7.6.1.3.25 PCMZ: PCM Zero Output Enable
          26. 7.6.1.3.26 R: Read Mode Select
          27. 7.6.1.3.27 ZFGx: Zero-Detection Flag
          28. 7.6.1.3.28 Read Mode Select
          29. 7.6.1.3.29 ID[4:0]: Device ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Connection Diagram in PCM Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 I/V Section
          2. 8.2.1.2.2 Differential Section
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application for External Digital Filter Interface
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Application for Interfacing With an External Digital Filter
          2. 8.2.2.2.2 Pin Assignment When Using the External Digital Filter Interface
          3. 8.2.2.2.3 Audio Format
          4. 8.2.2.2.4 System Clock (SCK) and Interface Timing
          5. 8.2.2.2.5 Functions Available in the External Digital Filter Mode
            1. 8.2.2.2.5.1 FMT[2:0]: Audio Data Format Selection
            2. 8.2.2.2.5.2 OS[1:0]: ΔΣ Modulator Oversampling Rate Selection
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Application for DSD Format (DSD Mode) Interface
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Features
          2. 8.2.3.2.2 Pin Assignment When Using DSD Format Interface
          3. 8.2.3.2.3 Requirements for System Clock
          4. 8.2.3.2.4 DSD Mode Configuration and Function Controls
            1. 8.2.3.2.4.1 Configuration for the DSD Interface Mode
            2. 8.2.3.2.4.2 DMF[1:0]: Analog-FIR Performance Selection
            3. 8.2.3.2.4.3 OS[1:0]: Analog-FIR Operation-Speed Selection
        3. 8.2.3.3 Application Curves
      4. 8.2.4 TDMCA Interface Format
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1  TDMCA Mode Determination
          2. 8.2.4.2.2  TDMCA Terminals
          3. 8.2.4.2.3  Device ID Determination
          4. 8.2.4.2.4  TDMCA Frame
          5. 8.2.4.2.5  Command Field
            1. 8.2.4.2.5.1 Bit 31: Device ID Enable Flag
            2. 8.2.4.2.5.2 Bit 30: Extended Command Enable Flag
            3. 8.2.4.2.5.3 Bit 29: Daisy-Chain Selection Flag
            4. 8.2.4.2.5.4 Bits[28:24]: Device ID
            5. 8.2.4.2.5.5 Bit 23: Command Read/Write flag
            6. 8.2.4.2.5.6 Bits[22:16]: Register ID
            7. 8.2.4.2.5.7 Bits[15:8]: Command data
            8. 8.2.4.2.5.8 Bits[7:0]: Not used
          6. 8.2.4.2.6  Extended Command Field
          7. 8.2.4.2.7  Audio Fields
          8. 8.2.4.2.8  TDMCA Register Requirements
          9. 8.2.4.2.9  Register Write/Read Operation
          10. 8.2.4.2.10 TDMCA Mode Operation
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range, unless otherwise noted.
MIN MAX UNIT
Supply voltage VCC1, VCC2L, VCC2R –0.3 6.5 V
VDD –0.3 4 V
Supply voltage differences VCC1, VCC2L, VCC2R –0.1 0.1 V
Ground voltage differences AGND1, AGND2, AGND3L, AGND3R, DGND –0.1 0.1 V
Digital input voltage LRCK, DATA, BCK, SCK, MSEL, RST, MS(2), MDI, MC, MDO(2), ZEROL(2), ZEROR(2) –0.3 6.5 V
ZEROL(3), ZEROR(3), MDO(3), MS(3) –0.3 (VDD + 0.3) < 4 V
Analog input voltage –0.3 (VCC + 0.3) < 6.5 V
Input current (any pins except supplies) –10 10 mA
Ambient temperature under bias –40 125 °C
Junction temperature 150 °C
Package temperature (IR reflow, peak) 260 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input mode or I2C mode.
(3) Output mode except for I2C mode.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Digital supply voltage 3.0 3.3 3.6 V
VCC1 Analog Supply Voltage 4.7525 5 5.25 V
VCC2L
VCC2R
Operating Temperature –25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) PCM1795 UNIT
DB (SSOP)
28 PINS
RθJA Junction-to-ambient thermal resistance 70.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 28.3
RθJB Junction-to-board thermal resistance 31.5
ψJT Junction-to-top characterization parameter 2.9
ψJB Junction-to-board characterization parameter 31.1
RθJC(bot) Junction-to-case (bottom) thermal resistance —
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit data, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 32 Bits
DATA FORMAT (PCM Mode)
Audio data interface format Standard, I2S, left-justified
Audio data bit length 16-, 24-, 32-bit selectable
Audio data format MSB first, twos complement
fS Sampling frequency 10 200 kHz
System clock frequency 128, 192, 256, 384, 512, 768 fS
DATA FORMAT (DSD Mode)
Audio data interface format DSD (direct stream digital)
Audio data bit length 1 Bit
fS Sampling frequency 2.8224 MHz
System clock frequency 2.8224 11.2986 MHz
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
VIH Input logic level 2 VDC
VIL 0.8 VDC
IIH Input logic current VIN = VDD 10 μA
IIL VIN = 0 V –10 μA
VOH Output logic level IOH = –2 mA 2.4 VDC
VOL IOL = 2 mA 0.4 VDC
DYNAMIC PERFORMANCE (PCM MODE)(1)(2)
THD+N at VOUT = 0 dB fS = 48 kHz 0.0005% 0.001%
fS = 96 kHz 0.001%
fS = 192 kHz 0.0015%
Dynamic range EIAJ, A-weighted, fS = 48 kHz 120 123 dB
EIAJ, A-weighted, fS = 96 kHz 123
EIAJ, A-weighted, fS = 192 kHz 123
Signal-to-noise ratio EIAJ, A-weighted, fS = 48 kHz 120 123 dB
EIAJ, A-weighted, fS = 96 kHz 123
EIAJ, A-weighted, fS = 192 kHz 123
Channel separation fS = 48 kHz 116 119 dB
fS = 96 kHz 118
fS = 192 kHz 117
Level linearity error VOUT = –120 dB ±1 dB
DYNAMIC PERFORMANCE (MONO MODE)(1)(2)(3)
THD+N at VOUT = 0 dB fS = 48 kHz 0.0005%
fS = 96 kHz 0.001%
fS = 192 kHz 0.0015%
Dynamic range EIAJ, A-weighted, fS = 48 kHz 126 dB
EIAJ, A-weighted, fS = 96 kHz 126
EIAJ, A-weighted, fS = 192 kHz 126
Signal-to-noise ratio EIAJ, A-weighted, fS = 48 kHz 126 dB
EIAJ, A-weighted, fS = 96 kHz 126
EIAJ, A-weighted, fS = 192 kHz 126
DSD MODE DYNAMIC PERFORMANCE (44.1 kHz, 64 fS)(1)(4)
THD+N at FS 2 V rms 0.0007%
Dynamic range –60 dB, EIAJ, A-weighted 122 dB
Signal-to-noise ratio EIAJ, A-weighted 122 dB
ANALOG OUTPUT
Gain error –7 ±2 7 % of FSR
Gain mismatch, channel-to-channel –3 ±0.5 3 % of FSR
Bipolar zero error At BPZ –2 ±0.5 2 % of FSR
Output current Full-scale (0 dB) 4 mAPP
Center current At BPZ –3.5 mA
DIGITAL FILTER PERFORMANCE
De-emphasis error ±0.1 dB
FILTER CHARACTERISTICS–1: SHARP ROLL-OFF
Passband ±0.0002 dB 0.454 fS
–3 dB 0.49
Stop band 0.546 fS
Passband ripple ±0.0002 dB
Stop-band attenuation Stop band = 0.546 fS –98 dB
Delay time 38/fS s
FILTER CHARACTERISTICS–2: SLOW ROLL-OFF
Passband ±0.001 dB 0.21 fS
–3 dB 0.448
Stop band 0.79 fS
Passband ripple ±0.001 dB
Stop-band attenuation Stop band = 0.732 fS –80 dB
Delay time 38/fS s
POWER-SUPPLY REQUIREMENTS
VDD Voltage range 3 3.3 3.6 VDC
VCC1 4.75 5 5.25 VDC
VCC2L
VCC2R
IDD Supply current(5) fS = 48 kHz 6 8 mA
fS = 96 kHz 11
fS = 192 kHz 21
ICC fS = 44.1 kHz 18 23
fS = 96 kHz 19
fS = 192 kHz 20
Power dissipation(5) fS = 48 kHz 110 141 mW
fS = 96 kHz 131
fS = 192 kHz 166
TEMPERATURE RANGE
Operating temperature –25 +85 °C
(1) Filter condition:
THD+N: 20-Hz high-pass filter (HPF), 20-kHz AES17 low-pass filter (LPF)
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in the averaging mode.
(2) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 53.
(3) Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 55.
(4) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 54.
(5) Input is bipolar zero (BPZ) data.

6.6 Timing Requirements

MIN MAX UNIT
f(SCL) SCL clock frequency Standard 100 kHz
Fast 400
t(BUF) Bus free time between stop and start conditions Standard 4.7 μs
Fast 1.3
t(LOW) Low period of the SCL clock Standard 4.7 μs
Fast 1.3
t(HI) High period of the SCL clock Standard 4 μs
Fast 600 ns
t(RS-SU) Setup time for (repeated) start condition Standard 4.7 μs
Fast 600 ns
t(S-HD) Hold time for (repeated) start condition Standard 4 μs
t(RS-HD) Fast 600 ns
t(D-SU) Data setup time Standard 250 ns
Fast 100
t(D-HD) Data hold time Standard 0 900 ns
Fast 0 900
t(SCL-R) Rise time of SCL signal Standard 20 + 0.1 CB 1000 ns
Fast 20 + 0.1 CB 300
t(SCL-R1) Rise time of SCL signal after a repeated start condition and after an acknowledge bit Standard 20 + 0.1 CB 1000 ns
Fast 20 + 0.1 CB 300
t(SCL-F) Fall time of SCL signal Standard 20 + 0.1 CB 1000 ns
Fast 20 + 0.1 CB 300
t(SDA-R) Rise time of SDA signal Standard 20 + 0.1 CB 1000 ns
Fast 20 + 0.1 CB 300
t(SDA-F) Fall time of SDA signal Standard 20 + 0.1 CB 1000 ns
Fast 20 + 0.1 CB 300
t(P-SU) Setup time for stop condition Standard 4 μs
Fast 600 ns
C(B) Capacitive load for SDA and SCL line 400 pF
t(SP) Pulse duration of suppressed spike Fast 50 ns
VNH Noise margin at high level for each connected device (including hysteresis) 0.2 VDD V
PCM1795 tim_les248.gifFigure 1. Timing Definition on the I2C Bus

6.7 Typical Characteristics

6.7.1 Digital Filter

PCM1795 tc_digi_amp-frq_fresp_sharp_les248.gifFigure 2. Amplitude vs Frequency
PCM1795 tc_digi_amp-frq_fresp_slow_les248.gifFigure 4. Amplitude vs Frequency
PCM1795 tc_digi_amp-frq_pass_les248.gifFigure 3. Amplitude vs Frequency
PCM1795 tc_digi_amp-frq_tchara_les248.gifFigure 5. Amplitude vs Frequency

6.7.2 Digital Filter: De-Emphasis Filter

PCM1795 tc_digi_delev-frq_32k_les248.gifFigure 6. De-Emphasis Level vs Frequency
PCM1795 tc_digi_delev-frq_44k_les248.gifFigure 8. De-Emphasis Level vs Frequency
PCM1795 tc_digi_delev-frq_48k_les248.gifFigure 10. De-Emphasis Level vs Frequency
PCM1795 tc_digi_derr-frq_32k_les248.gifFigure 7. De-Emphasis Error vs Frequency
PCM1795 tc_digi_derr-frq_44k_les248.gifFigure 9. De-Emphasis Error vs Frequency
PCM1795 tc_digi_derr-frq_48k_les248.gifFigure 11. De-Emphasis Error vs Frequency

6.7.3 Analog Dynamic Performance: Supply Voltage Characteristics

PCM mode, TA = +25°C, and VDD = 3.3 V; measured with circuit shown in Figure 53, unless otherwise noted.

PCM1795 tc_ana_thdn-vs_les248.gifFigure 12. THD+N vs Supply Voltage
PCM1795 tc_ana_snr-vs_les248.gifFigure 14. SNR vs Supply Voltage
PCM1795 tc_ana_range-vs_les248.gifFigure 13. Dynamic Range vs Supply Voltage
PCM1795 tc_ana_chsep-vs_les248.gifFigure 15. Channel Separation vs Supply Voltage

6.7.4 Analog Dynamic Performance: Temperature Characteristics

PCM mode, VDD = 3.3 V, and VCC = 5 V; measured with circuit shown in Figure 53, unless otherwise noted.

PCM1795 tc_ana_thdn-tmp_les248.gifFigure 16. THD+N vs Free-Air Temperature
PCM1795 tc_ana_snr-tmp_les248.gifFigure 18. SNR vs Free-Air Temperature
PCM1795 tc_ana_amp-frq_20k_les248.gifFigure 20. Amplitude vs Frequency
(Measurement Circuit: Figure 53)
PCM1795 tc_n144_ospec_les248.gifFigure 22. Amplitude vs Frequency
(Measurement Circuit: Figure 53)
PCM1795 tc_ana_thdn-ilev_les248.gifFigure 24. THD+N vs Input Level
(Measurement Circuit: Figure 53)
PCM1795 tc_ana_range-tmp_les248.gifFigure 17. Dynamic Range vs Free-Air Temperature
PCM1795 tc_ana_chsep-tmp_les248.gifFigure 19. Channel Separation vs Free-Air Temperature
PCM1795 tc_ana_amp-frq_100k_les248.gifFigure 21. Amplitude vs Frequency
(Measurement Circuit: Figure 53)
PCM1795 tc_n150_ospec_les248.gifFigure 23. Amplitude vs Frequency
(Measurement Circuit: Figure 53)
PCM1795 tc_ana_amp-frq_dsd_les248.gifFigure 25. Amplitude vs Frequency
(Measurement Circuit: Figure 54)

6.7.5 Analog FIR Filter performance in DSD Mode

All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.

PCM1795 tc_fir_g-frq_dsd1_lo_les248.gifFigure 26. Gain vs Frequency
PCM1795 tc_fir_g-frq_dsd2_lo_les248.gifFigure 28. Gain vs Frequency
PCM1795 tc_fir_g-frq_dsd3_lo_les248.gifFigure 30. Gain vs Frequency
PCM1795 tc_fir_g-frq_dsd4_lo_les248.gifFigure 32. Gain vs Frequency
PCM1795 tc_fir_g-frq_dsd1_hi_les248.gifFigure 27. Gain vs Frequency(1)
(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
PCM1795 tc_fir_g-frq_dsd2_hi_les248.gifFigure 29. Gain vs Frequency(1)
PCM1795 tc_fir_g-frq_dsd3_hi_les248.gifFigure 31. Gain vs Frequency(1)
PCM1795 tc_fir_g-frq_dsd4_hi_les248.gifFigure 33. Gain vs Frequency(1)