SLES177B April   2006  – August 2015 PCM1808

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 System Clock
      3. 7.3.3 Synchronization With Digital Audio System
      4. 7.3.4 Power On
      5. 7.3.5 Serial Audio Data Interface
        1. 7.3.5.1 Interface Mode
          1. 7.3.5.1.1 Master Mode
          2. 7.3.5.1.2 Slave Mode
        2. 7.3.5.2 Data Format
        3. 7.3.5.3 Interface Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fade-In and Fade-Out Functions
      2. 7.4.2 Clock-Halt Power-Down and Reset Function
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Control Pins
        2. 8.2.2.2 Master Clock
        3. 8.2.2.3 DSP or Audio Processor
        4. 8.2.2.4 Input Filters
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VCC, VDD Pins
      2. 10.1.2 AGND, DGND Pins
      3. 10.1.3 VINL, VINR Pins
      4. 10.1.4 VREF Pin
      5. 10.1.5 DOUT Pin
      6. 10.1.6 System Clock
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The PCM1808 device is suitable for wide variety of cost-sensitive consumer applications requiring good performance and operation with a 5-V analog supply and 3.3-V digital supply.

8.2 Typical Application

PCM1808 typapp_circuit_cont_diag_sles177.gif
1. C1, C2: A 1-μF electrolytic capacitor gives 2.7 Hz (τ = 1 μF × 60 kΩ) cutoff frequency for the input HPF in normal operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period.
2. C3, C4: Bypass capacitors, 0.1-μF ceramic and 10-μF electrolytic, depending on layout and power supply
3. C5: Recommended capacitors are 0.1-μF ceramic and 10-μF electrolytic.
4. X1: X1 masks the system clock input when using the clock-halt reset function with external control.
5. Optional external antialiasing filter could be required, depending on the application.
Figure 26. Typical Circuit Connection Diagram

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 4 as the input parameters.

Table 4. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Analog input voltage range 0 Vp-p to 3 Vp-p
Output PCM audio data
System clock input frequency 2.048 MHz to 49.152 MHz
Output sampling frequency 8 kHz to 96 kHz
Power supply 3.3 V and 5 V

8.2.2 Detailed Design Procedure

8.2.2.1 Control Pins

The control pins FMT, MD0, and MD1 should be controlled either by biasing with a 10 kΩ resister to VDD or GND, or by driving with GPIO from the DSP or audio processor.

8.2.2.2 Master Clock

In this application of the PCM1808 device, a PLL170X series device is used as the master clock source to drive both the PCM1808 and the DSP or audio processor synchronously. With the addition of the AND gate, the operation of the PCM1808 device can be halted by control of the MASK bit. A crystal that operates at the standard audio multiples can also be used.

8.2.2.3 DSP or Audio Processor

In this application, the DSP or audio processor is acting as the audio master, and the PCM1808 is acting as the audio slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1808 can use to process audio signals.

8.2.2.4 Input Filters

For the analog input circuit, an ac coupling capacitor should be placed in series with the input. This will remove the dc component of the input signal. An RC filter can also be implemented to filter out-of-band noise to reduce aliasing. The equation below can be used to calculate the cutoff frequency of the optional RC filter for the input.

Equation 1. PCM1808 eq01_SLES177.gif

8.2.3 Application Curve

PCM1808 sles177_g013.gif Figure 27. Output Spectrum