SBASAH4A April   2022  – September 2022 PCM1820-Q1 , PCM1821-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 7.4 Electrical Characteristics
    6. 7.5 Timing Requirements: TDM, I2S or LJ Interface
    7. 7.6 Switching Characteristics: TDM, I2S or LJ Interface
    8. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Inter IC Sound (I2S) Interface

The standard I2S protocol is defined for only two channels: left and right. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. The MSB of the right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is transmitted on the rising edge of BCLK. Figure 8-5 and Figure 8-6 show the protocol timing for I2S operation in slave and master mode of operation.

GUID-DB0E832A-867F-4D8C-9F09-D6D526B6E4E9-low.gifFigure 8-5 I2S Mode Protocol Timing in Slave Mode
GUID-4D877073-24AA-4C27-974A-47844F8AAC85-low.gifFigure 8-6 I2S Protocol Timing In Master Mode

For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the 32-bits word length of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the 32-bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.