SBASAH5A April   2022  – September 2022 PCM1822-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 7.4 Electrical Characteristics
    6. 7.5 Timing Requirements: TDM, I2S or LJ Interface
    7. 7.6 Switching Characteristics: TDM, I2S or LJ Interface
    8. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC CONFIGURATION
AC input impedance Input pins INxP or INxM 2.5 kΩ
ADC PERFORMANCE FOR LINE, MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Full-scale AC signal voltage Differential/Single Ended AC-coupled input 1 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential/single-ended input selected and AC signal shorted to ground, DRE enabled (DRE_LVL =
–36 dB, DRE_MAXGAIN = 18 dB)		 110 117 dB
IN1 differential/single-ended input selected and AC signal shorted to ground, DRE disabled 105 111
DR Dynamic range, A-weighted(2) IN1 differential/single-ended input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 18 dB) 117 dB
IN1 differential/single-ended input selected and –60-dB full-scale AC signal input, DRE disabled 111
THD+N Total harmonic distortion(2)(3) IN1 differential/single-ended input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL =
–36 dB, DRE_MAXGAIN = 18 dB)		 –95 –80 dB
IN1 differential/single-ended input selected and –1-dB full-scale AC signal input, DRE disabled –95
ADC OTHER PARAMETERS
Output data sample rate 7.35 192 kHz
Output data sample word length 32 Bits
Interchannel isolation –1-dB full-scale AC-signal input to non measurement channel –124 dB
Interchannel gain mismatch –6-dB full-scale AC-signal input 0.1 dB
Gain drift(4) Across temperature range -40°C to 125°C 50 ppm/°C
Interchannel phase mismatch 1-kHz sinusoidal signal 0.02 Degrees
Phase drift(5) 1-kHz sinusoidal signal, across temperature range -40°C to 125°C 0.0005 Degrees/°C
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 102 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 100-mVPP, 1-kHz signal on both pins and measure level at output 45 dB
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except FMT0, IOVDD 1.8-V operation –0.3 0.30 × IOVDD V
All digital pins except FMT0, IOVDD 3.3-V operation –0.3 0.8
FMT0 Pin –0.3 0.8 V
VIH High-level digital input logic voltage threshold All digital pins except FMT0, IOVDD 1.8-V operation 0.7 × IOVDD IOVDD + 0.3 V
All digital pins except FMT0, IOVDD 3.3-V operation 2.1 IOVDD + 0.3
FMT0 Pin 2.1 AVDD + 0.3 V
VOL Low-level digital output voltage All digital pins, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins, IOH = 2 mA, IOVDD 3.3-V operation 2.4
IIH Input logic-high leakage for digital inputs All digital pins except FMT0, input = IOVDD –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins except FMT0, input = 0 V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs FMT0 Pin, input = AVDD All digital pins, input = IOVDD –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs FMT0 Pin, input = 0 V All digital pins, input = 0 V –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption with all Clocks disabled AVDD = 3.3 V, internal AREG 0.5 mA
IIOVDD All external clocks stopped, IOVDD = 3.3 V 0.5 µA
IIOVDD All external clocks stopped, IOVDD = 1.8 V 0.3
IAVDD Current consumption with ADC 2-channel operating at fS 16-kHz, BCLK = 256 × fS and DRE disabled AVDD = 3.3 V, internal AREG 11.9 mA
IIOVDD IOVDD = 3.3 V 0.05
IIOVDD IOVDD = 1.8 V 0.02 
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, BCLK = 256 × fS and DRE disabled AVDD = 3.3 V, internal AREG 12.9 mA
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, BCLK = 256 × fS and DRE enabled AVDD = 3.3 V, internal AREG 14 mA
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with a 20-kHz, low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with a low-voltage-coefficient.
(4) Gain drift =gain_variation(in temperature range)/ typical gain value(gain at room temperature) / temperature range × 106 measured with gain in linear scale.
(5) Phase drift =phase_deviation(in temperature range)/ (temperature range).