The standard LJ protocol is defined for only two channels: left and right. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In controller mode, FSYNC is transmitted on the rising edge of BCLK. Figure 6-7 and Figure 6-8 illustrate the protocol timing for LJ operation in target and controller mode of operation.

Figure 6-7 LJ Mode Protocol Timing In Target Mode

Figure 6-8 LJ Mode Protocol Timing In Controller Mode

For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than, or equal to, the number of active output channels (including left and right slots) times the 32-bit word length of the output channel data. The device FSYNC high pulse must be atleast Word length(32-bits) times number of active left channels, BCLK cycles wide. Similarly, the FSYNC low pulse must be atleast Word length(32-bits) times number of active right channels, BCLK cycles wide. The device transmits zero data value on SDOUT for the extra unused bit clock cycles.