SLAS831D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
SIGDET_TRIG_MASK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4R | CH4L | CH3R | CH3L | CH2R | CH2L | CH1R | CH1L |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH4R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 4 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
6 | CH4L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 4 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
5 | CH3R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 3 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
4 | CH3L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 3 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
3 | CH2R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 2 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
2 | CH2L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 2 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
1 | CH1R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 1 Right
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
0 | CH1L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 1 Left
All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |