The PCM270xC are TI's single-chip USB stereo audio digital-to-analog converters (DACs) with USB 2.0 compliant full-speed protocol controller and S/PDIF. The USB-protocol controller works with no software code, but USB descriptors can be modified in some areas (for example, vendor ID/product ID) through the use of an external ROM (PCM2704C and PCM2706C) or serial peripheral interface (SPI) (PCM2705C and PCM2707C). The PCM270xC also employ SpAct™ architecture, TI's unique system that recovers the audio clock from USB packet data. On-chip analog phase-locked loops (PLLs) with SpAct enable playback with low clock jitter.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
PCM2704C | SSOP (28) | 5.30 mm × 10.20 mm |
PCM2705C | ||
PCM2706C | TQFP (32) | 7.00 mm × 7.00 mm |
PCM2707C |
Changes from A Revision (July 2012) to B Revision
Changes from * Revision (August 2011) to A Revision
FEATURE | PCM2704C | PCM2705C | PCM2706C | PCM2707C |
---|---|---|---|---|
Supply Voltage (V) | 3.3, 5 | 3.3, 5 | 3.3, 5 | 3.3, 5 |
Control Interface | HID | HID, SPI | HID, SPI | HID, SPI |
Additional Features | S/PDIF Output HP Output Ext. ROM I/F |
S/PDIF Output HP Output |
S/PDIF Output HP Output Ext. ROM I/F |
S/PDIF Output HP Output |
Package Group | SSOP | SSOP | TQFP | TQFP |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGNDL | 12 | — | Analog ground for headphone amplifier of L-channel |
AGNDR | 17 | — | Analog ground for headphone amplifier of R-channel |
CK | 2 | O | Clock output for external ROM (PCM2704C). Must be left open (PCM2705C). |
D+ | 9 | I/O | USB differential input/output plus(1) |
D– | 8 | I/O | USB differential input/output minus(1) |
DGND | 6 | — | Digital ground |
DOUT | 5 | O | S/PDIF output |
DT | 3 | I/O | Data input/output for external ROM (PCM2704C). Must be left open with pullup resistor (PCM2705C).(1) |
HID0/MS | 22 | I | HID key state input (mute), active high (PCM2704C). MS input (PCM2705C)(3) |
HID1/MC | 23 | I | HID key state input (volume up), active high (PCM2704C). MC input (PCM2705C)(3) |
HID2/MD | 24 | I | HID key state input (volume down), active high (PCM2704C). MD input (PCM2705C)(3) |
HOST | 21 | I | Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered operation (low: 100 mA, high: 500 mA).(2) |
PGND | 19 | — | Analog ground for DAC, OSC, and PLL |
PSEL | 4 | I | Power source select (low: self-power, high: bus-power)(1) |
SSPND | 27 | O | Suspend flag, active low (low: suspend, high: operational) |
TEST0 | 26 | I | Test pin. Must be set high(1) |
TEST1 | 25 | I | Test pin. Must be set high(1) |
VBUS | 10 | — | Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation. |
VCCL | 13 | — | Analog power supply for headphone amplifier of L-channel(4) |
VCCP | 20 | — | Analog power supply for DAC, OSC, and PLL(4) |
VCCR | 16 | — | Analog power supply for headphone amplifier of R-channel(4) |
VCOM | 18 | — | Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND. |
VDD | 7 | — | Digital power supply(4) |
VOUTL | 14 | O | DAC analog output for L-channel |
VOUTR | 15 | O | DAC analog output for R-channel |
XTI | 28 | I | Crystal oscillator input(1) |
XTO | 1 | O | Crystal oscillator output |
ZGND | 11 | — | Ground for internal regulator |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGNDL | 26 | — | Analog ground for headphone amplifier of L-channel |
AGNDR | 31 | — | Analog ground for headphone amplifier of R-channel |
CK | 14 | O | Clock output for external ROM (PCM2706C). Must be left open (PCM2707C). |
D+ | 23 | I/O | USB differential input/output plus(1) |
D– | 22 | I/O | USB differential input/output minus(1) |
DGND | 20 | — | Digital ground |
DOUT | 17 | O | S/PDIF output/I2S data output |
DT | 15 | I/O | Data input/output for external ROM (PCM2706C). Must be left open with pullup resistor (PCM2707C).(1) |
FSEL | 9 | I | Function select (low: I2S data output, high: S/PDIF output)(1) |
FUNC0 | 5 | I/O | HID key state input (next track), active high (FSEL = 1). I2S LR clock output (FSEL = 0).(3) |
FUNC1 | 19 | I/O | HID key state input (previous track), active high (FSEL = 1). I2S bit clock output (FSEL = 0).(3) |
FUNC2 | 18 | I/O | HID key state input (stop), active high (FSEL = 1). I2S system clock output (FSEL = 0).(3) |
FUNC3 | 4 | I | HID key state input (play/pause), active high (FSEL = 1). I2S data input (FSEL = 0).(3) |
HID0/MS | 6 | I | HID key state input (mute), active high (PCM2706C). MS input (PCM2707C).(3) |
HID1/MC | 7 | I | HID key state input (volume up), active high (PCM2706C). MC input (PCM2707C).(3) |
HID2/MD | 8 | I | HID key state input (volume down), active high (PCM2706C). MD input (PCM2707C).(3) |
HOST | 3 | I | Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered operation. (low: 100 mA, high: 500 mA).(2) |
PGND | 1 | — | Analog ground for DAC, OSC, and PLL |
PSEL | 16 | I | Power source select (low: self-power, high: bus-power)(1) |
SSPND | 11 | O | Suspend flag, active low (low: suspend, high: operational) |
TEST | 10 | I | Test pin. Must be set high(1) |
VBUS | 24 | — | Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation. |
VCCL | 27 | — | Analog power supply for headphone amplifier of L-channel(4) |
VCCP | 2 | — | Analog power supply for DAC, OSC, and PLL(4) |
VCCR | 30 | — | Analog power supply for headphone amplifier of R-channel(4) |
VCOM | 32 | — | Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND. |
VDD | 21 | — | Digital power supply(4) |
VOUTL | 28 | O | DAC analog output for L-channel |
VOUTR | 29 | O | DAC analog output for R-channel |
XTI | 12 | I | Crystal oscillator input(1) |
XTO | 13 | O | Crystal oscillator output |
ZGND | 25 | — | Ground for internal regulator |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | VBUS | –0.3 | 6.5 | V |
VCCP, VCCL, VCCR, VDD | –0.3 | 4 | V | |
Supply voltage differences | VCCP, VCCL, VCCR, VDD | ±0.1 | V | |
Ground voltage differences | PGND, AGNDL, AGNDR, DGND, ZGND | ±0.1 | V | |
Digital input voltage | HOST | –0.3 | 6.5 | V |
D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT, PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3 | –0.3 | (VDD + 0.3) < 4 | V | |
Analog input voltage | VCOM | –0.3 | (VCCP + 0.3) < 4 | V |
VOUTR | –0.3 | (VCCR + 0.3) < 4 | V | |
VOUTL | –0.3 | (VCCL + 0.3) < 4 | V | |
Input current (any pins except supplies) | ±10 | mA | ||
Ambient temperature under bias | –40 | 125 | °C | |
Junction temperature | 150 | °C | ||
Package temperature (IR reflow, peak) | 260 | °C | ||
Storage temperature, Tstg | –55 | 150 | °C |
MAX | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±3000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage | VBUS | 4.35 | 5 | 5.25 | V |
VCCP, VCCL, VCCR, VDD | 3 | 3.3 | 3.6 | ||
Digital input logic level | TTL-compatible | ||||
Digital input clock frequency | 11.994 | 12 | 12.006 | MHz | |
Analog output load resistance | 16 | 32 | Ω | ||
Analog output load capacitance | 100 | pF | |||
Digital output load capacitance | 20 | pF | |||
Operating free-air temperature, TA | –25 | 85 | °C |
THERMAL METRIC(1) | PCM2704C, PCM2705C | UNIT | |
---|---|---|---|
DB (SSOP) | |||
28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 68.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 27.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 2.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 29.1 | °C/W |
THERMAL METRIC(1) | PCM2706C, PCM2707C | UNIT | |
---|---|---|---|
PJT (TQFP) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 68.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 27.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 2.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 29.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT LOGIC | |||||||
VIH | Input logic high level | 2 | 3.3 | VDC | |||
Input logic high level(1) | 2 | 5.5 | |||||
VIL | Input logic low level | –0.3 | 0.8 | VDC | |||
Input logic low level(1) | –0.3 | 0.8 | |||||
IIH | Input logic high current(2) | VIN = 3.3 V | ±10 | μA | |||
Input logic high current | VIN = 3.3 V | 65 | 100 | ||||
IIL | Input logic low current(2) | VIN = 0 V | ±10 | μA | |||
Input logic low current | VIN = 0 V | ±10 | |||||
OUTPUT LOGIC | |||||||
VOH | Output logic high level(3) | IOH = –2 mA | 2.8 | VDC | |||
Output logic high level | IOH = –2 mA | 2.4 | |||||
VOL | Output logic low level(3) | IOL = 2 mA | 0.3 | VDC | |||
Output logic low level | IOL = 2 mA | 0.4 | |||||
CLOCK FREQUENCY | |||||||
Input clock frequency, XTI | 11.994 | 12 | 12.006 | MHz | |||
ƒS | Sampling frequency | 32 44.1 48 |
kHz | ||||
DAC CHARACTERISTICS | |||||||
Resolution | 16 | bits | |||||
Audio data channel | 1, 2 | channel | |||||
DC ACCURACY | |||||||
Gain mismatch, channel-to-channel | ±2 | ±8 | % of FSR | ||||
Gain error | ±2 | ±8 | % of FSR | ||||
Bipolar zero error | ±3 | ±6 | % of FSR | ||||
DYNAMIC PERFORMANCE (4) | |||||||
THD + N | Total harmonic distortion + noise | Line (5) | RL > 10 kΩ, self-powered, VOUT = 0 dB | 0.006% | 0.01% | ||
RL > 10 kΩ, bus-powered, VOUT = 0 dB | 0.012% | 0.02% | |||||
Headphone | RL = 32 Ω, self- or bus-powered, VOUT = 0 dB | 0.025% | |||||
THD + N | Total harmonic distortion + noise | VOUT = –60 dB | 2% | ||||
Dynamic range | EIAJ, A-weighted | 90 | 98 | dB | |||
SNR | Signal-to-noise ratio | EIAJ, A-weighted | 90 | 98 | dB | ||
Channel separation | 60 | 70 | dB | ||||
ANALOG OUTPUT | |||||||
Output voltage | 0.55 VCCL
0.55 VCCR |
VPP | |||||
Center voltage | 0.5 VCCP | V | |||||
Load impedance | Line | AC-coupling | 10 | kΩ | |||
Headphone | AC-coupling | 16 | 32 | Ω | |||
LPF frequency response | –3 dB | 140 | kHz | ||||
ƒ = 20 kHz | –0.1 | dB | |||||
DIGITAL FILTER PERFORMANCE | |||||||
Passband | 0.454 ƒS | Hz | |||||
Stop band | 0.546 ƒS | Hz | |||||
Passband ripple | ±0.04 | dB | |||||
Stop band attenuation | –50 | dB | |||||
Delay time | 20 / ƒS | s | |||||
POWER SUPPLY REQUIREMENTS | |||||||
Voltage range | VBUS | Bus-powered | 4.35 | 5 | 5.25 | VDC | |
VCCP, VCCL, VCCR, VDD | Self-powered | 3 | 3.3 | 3.6 | |||
Supply current | Line | DAC operation | 23 | 30 | mA | ||
Headphone | DAC operation (RL = 32 Ω) | 35 | 46 | ||||
Line/headphone | Suspend mode (6) | 150 | 190 | μA | |||
Power dissipation (self-powered) | Line | DAC operation | 76 | 108 | mW | ||
Headphone | DAC operation (RL = 32 Ω) | 116 | 166 | ||||
Line/headphone | Suspend mode (6) | 495 | 684 | μW | |||
Power dissipation (bus-powered) | Line | DAC operation | 115 | 158 | mW | ||
Headphone | DAC operation (RL = 32 Ω) | 175 | 242 | ||||
Line/headphone | Suspend mode (6) | 750 | 998 | μW | |||
Internal power-supply voltage (7) | VCCP, VCCL, VCCR, VDD | Bus-powered | 3.2 | 3.35 | 3.5 | VDC | |
TEMPERATURE RANGE | |||||||
Operating temperature | –25 | 85 | °C |
MIN | MAX | UNIT | ||
---|---|---|---|---|
t(BCY) | BCK pulse cycle time | 300 | ns | |
t(BCH) | BCK pulse duration, high | 100 | ns | |
t(BCL) | BCK pulse duration, low | 100 | ns | |
t(BL) | LRCK delay time from BCK falling edge | –20 | 40 | ns |
t(BD) | DOUT delay time from BCK falling edge | –20 | 40 | ns |
t(LD) | DOUT delay time from LRCK edge | –20 | 40 | ns |
t(DS) | DIN setup time | 20 | ns | |
t(DH) | DIN hold time | 20 | ns |
MIN | MAX | UNIT | ||
---|---|---|---|---|
t(SLL), t(SLH) | LRCK delay time from SYSCK rising edge | –5 | 10 | ns |
t(SBL), t(SBH) | BCK delay time from SYSCK rising edge | –5 | 10 | ns |
MIN | MAX | UNIT | ||
---|---|---|---|---|
ƒ(CK) | CK clock frequency | 100 | kHz | |
t(BUF) | Bus free time between a STOP and a START condition | 4.7 | μs | |
t(LOW) | Low period of the CK clock | 4.7 | μs | |
t(HI) | High period of the CK clock | 4 | μs | |
t(RS-SU) | Setup time for START/repeated START condition | 4.7 | μs | |
t(S-HD)
t(RS-HD) |
Hold time for START/repeated START condition | 4 | μs | |
t(D-SU) | Data setup time | 250 | ns | |
t(D-HD) | Data hold time | 0 | 900 | ns |
t(CK-R) | Rise time of CK signal | 20 + 0.1 CB | 1000 | ns |
t(CK-F) | Fall time of CK signal | 20 + 0.1 CB | 1000 | ns |
t(DT-R) | Rise time of DT signal | 20 + 0.1 CB | 1000 | ns |
t(DT-F) | Fall time of DT signal | 20 + 0.1 CB | 1000 | ns |
t(P-SU) | Setup time for STOP condition | 4 | μs | |
CB | Capacitive load for DT and CK lines | 400 | pF | |
VNH | Noise margin at high level for each connected device (including hysteresis) | 0.2 VDD | V |
MIN | MAX | UNIT | ||
---|---|---|---|---|
t(MCY) | MC pulse cycle time | 100 | ns | |
t(MCL) | MC low-level time | 50 | ns | |
t(MCH) | MC high-level time | 50 | ns | |
t(MHH) | MS high-level time | 100 | ns | |
t(MLS) | MS falling edge to MC rising edge | 20 | ns | |
t(MLH) | MS hold time | 20 | ns | |
t(MDH) | MD hold time | 15 | ns | |
t(MDS) | MD setup time | 20 | ns |