SBASAU5 March 2024 PCM5140-Q1
PRODUCTION DATA
This section describes the device configuration registers for page 0.
ADDRESS | REGISTER | DESCRIPTION | SECTION |
---|---|---|---|
0x00 | PAGE_CFG | Device page register | Section 7.6.1.1.1 |
0x01 | SW_RESET | Software reset register | Section 7.6.1.1.2 |
0x02 | SLEEP_CFG | Sleep mode register | Section 7.6.1.1.3 |
0x05 | SHDN_CFG | Shutdown configuration register | Section 7.6.1.1.4 |
0x07 | ASI_CFG0 | ASI configuration register 0 | Section 7.6.1.1.5 |
0x08 | ASI_CFG1 | ASI configuration register 1 | Section 7.6.1.1.6 |
0x09 | ASI_CFG2 | ASI configuration register 2 | Section 7.6.1.1.7 |
0x0B | ASI_CH1 | Channel 1 ASI slot configuration register | Section 7.6.1.1.8 |
0x0C | ASI_CH2 | Channel 2 ASI slot configuration register | Section 7.6.1.1.9 |
0x0D | ASI_CH3 | Channel 3 ASI slot configuration register | Section 7.6.1.1.10 |
0x0E | ASI_CH4 | Channel 4 ASI slot configuration register | Section 7.6.1.1.11 |
0x0F | ASI_CH5 | Channel 5 ASI slot configuration register | Section 7.6.1.1.12 |
0x10 | ASI_CH6 | Channel 6 ASI slot configuration register | Section 7.6.1.1.13 |
0x11 | ASI_CH7 | Channel 7 ASI slot configuration register | Section 7.6.1.1.14 |
0x12 | ASI_CH8 | Channel 8 ASI slot configuration register | Section 7.6.1.1.15 |
0x13 | MST_CFG0 | ASI master mode configuration register 0 | Section 7.6.1.1.16 |
0x14 | MST_CFG1 | ASI master mode configuration register 1 | Section 7.6.1.1.17 |
0x15 | ASI_STS | ASI bus clock monitor status register | Section 7.6.1.1.18 |
0x16 | CLK_SRC | Clock source configuration register 0 | Section 7.6.1.1.19 |
0x1F | PDMCLK_CFG | PDM clock generation configuration register | Section 7.6.1.1.20 |
0x20 | PDMIN_CFG | PDM DINx sampling edge register | Section 7.6.1.1.21 |
0x21 | GPIO_CFG0 | GPIO configuration register 0 | Section 7.6.1.1.22 |
0x22 | GPO_CFG0 | GPO configuration register 0 | Section 7.6.1.1.23 |
0x23 | GPO_CFG1 | GPO configuration register 1 | Section 7.6.1.1.24 |
0x24 | GPO_CFG2 | GPO configuration register 2 | Section 7.6.1.1.25 |
0x25 | GPO_CFG3 | GPO configuration register 3 | Section 7.6.1.1.26 |
0x29 | GPO_VAL | GPIO, GPO output value register | Section 7.6.1.1.27 |
0x2A | GPIO_MON | GPIO monitor value register | Section 7.6.1.1.28 |
0x2B | GPI_CFG0 | GPI configuration register 0 | Section 7.6.1.1.29 |
0x2C | GPI_CFG1 | GPI configuration register 1 | Section 7.6.1.1.30 |
0x2F | GPI_MON | GPI monitor value register | Section 7.6.1.1.31 |
0x32 | INT_CFG | Interrupt configuration register | Section 7.6.1.1.32 |
0x33 | INT_MASK0 | Interrupt mask register 0 | Section 7.6.1.1.33 |
0x36 | INT_LTCH0 | Latched interrupt readback register 0 | Section 7.6.1.1.34 |
0x3B | BIAS_CFG | Bias and ADC configuration register | Section 7.6.1.1.35 |
0x3C | CH1_CFG0 | Channel 1 configuration register 0 | Section 7.6.1.1.36 |
0x3D | CH1_CFG1 | Channel 1 configuration register 1 | Section 7.6.1.1.37 |
0x3E | CH1_CFG2 | Channel 1 configuration register 2 | Section 7.6.1.1.38 |
0x3F | CH1_CFG3 | Channel 1 configuration register 3 | Section 7.6.1.1.39 |
0x40 | CH1_CFG4 | Channel 1 configuration register 4 | Section 7.6.1.1.40 |
0x41 | CH2_CFG0 | Channel 2 configuration register 0 | Section 7.6.1.1.41 |
0x42 | CH2_CFG1 | Channel 2 configuration register 1 | Section 7.6.1.1.42 |
0x43 | CH2_CFG2 | Channel 2 configuration register 2 | Section 7.6.1.1.43 |
0x44 | CH2_CFG3 | Channel 2 configuration register 3 | Section 7.6.1.1.44 |
0x45 | CH2_CFG4 | Channel 2 configuration register 4 | Section 7.6.1.1.45 |
0x46 | CH3_CFG0 | Channel 3 configuration register 0 | Section 7.6.1.1.46 |
0x47 | CH3_CFG1 | Channel 3 configuration register 1 | Section 7.6.1.1.47 |
0x48 | CH3_CFG2 | Channel 3 configuration register 2 | Section 7.6.1.1.48 |
0x49 | CH3_CFG3 | Channel 3 configuration register 3 | Section 7.6.1.1.49 |
0x4A | CH3_CFG4 | Channel 3 configuration register 4 | Section 7.6.1.1.50 |
0x4B | CH4_CFG0 | Channel 4 configuration register 0 | Section 7.6.1.1.51 |
0x4C | CH4_CFG1 | Channel 4 configuration register 1 | Section 7.6.1.1.52 |
0x4D | CH4_CFG2 | Channel 4 configuration register 2 | Section 7.6.1.1.53 |
0x4E | CH4_CFG3 | Channel 4 configuration register 3 | Section 7.6.1.1.54 |
0x4F | CH4_CFG4 | Channel 4 configuration register 4 | Section 7.6.1.1.55 |
0x52 | CH5_CFG2 | Channel 5 (PDM only) configuration register 2 | Section 7.6.1.1.56 |
0x53 | CH5_CFG3 | Channel 5 (PDM only) configuration register 3 | Section 7.6.1.1.57 |
0x54 | CH5_CFG4 | Channel 5 (PDM only) configuration register 4 | Section 7.6.1.1.58 |
0x57 | CH6_CFG2 | Channel 6 (PDM only) configuration register 2 | Section 7.6.1.1.59 |
0x58 | CH6_CFG3 | Channel 6 (PDM only) configuration register 3 | Section 7.6.1.1.60 |
0x59 | CH6_CFG4 | Channel 6 (PDM only) configuration register 4 | Section 7.6.1.1.61 |
0x5C | CH7_CFG2 | Channel 7 (PDM only) configuration register 2 | Section 7.6.1.1.62 |
0x5D | CH7_CFG3 | Channel 7 (PDM only) configuration register 3 | Section 7.6.1.1.63 |
0x5E | CH7_CFG4 | Channel 7 (PDM only) configuration register 4 | Section 7.6.1.1.64 |
0x61 | CH8_CFG2 | Channel 8 (PDM only) configuration register 2 | Section 7.6.1.1.65 |
0x62 | CH8_CFG3 | Channel 8 (PDM only) configuration register 3 | Section 7.6.1.1.66 |
0x63 | CH8_CFG4 | Channel 8 (PDM only) configuration register 4 | Section 7.6.1.1.67 |
0x6B | DSP_CFG0 | DSP configuration register 0 | Section 7.6.1.1.68 |
0x6C | DSP_CFG1 | DSP configuration register 1 | Section 7.6.1.1.69 |
0x6D | DRE_CFG0 | DRE configuration register 0 | Section 7.6.1.1.70 |
0x70 | AGC_CFG0 | AGC configuration register 0 | Section 7.6.1.1.71 |
0x73 | IN_CH_EN | Input channel enable configuration register | Section 7.6.1.1.72 |
0x74 | ASI_OUT_CH_EN | ASI output channel enable configuration register | Section 7.6.1.1.73 |
0x75 | PWR_CFG | Power up configuration register | Section 7.6.1.1.74 |
0x76 | DEV_STS0 | Device status value register 0 | Section 7.6.1.1.75 |
0x77 | DEV_STS1 | Device status value register 1 | Section 7.6.1.1.76 |
0x7E | I2C_CKSUM | I2C checksum register | Section 7.6.1.1.77 |
Table 7-54 lists the access codes used for the PCM5140-Q1 registers.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-W | R/W | Read or write |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |