PCM514x 2-VRMS DirectPath™, 112/106-dB Audio Stereo DAC With 32-bit, 384-kHz PCM Interface
- SLAS759B August 2012 – January 2016 PCM5141 , PCM5142
  
  PRODUCTION DATA.

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DATA SHEET

PCM514x 2-VRMS DirectPath™, 112/106-dB Audio Stereo DAC With 32-bit, 384-kHz PCM Interface

1 Features

Programmable miniDSP
Market-Leading Low Out-of-Band Noise
Selectable Digital-Filter Latency and Performance
No DC Blocking Capacitors Required
Integrated Negative Charge Pump
Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR
Integrated High-Performance Audio PLL With BCK Reference To Generate SCK Internally
Accepts 16-, 20-, 24-, And 32-Bit Audio Data
PCM Data Formats: I²S, Left-Justified, Right-Justified, TDM / DSP
SPI or I²C Control
Software or Hardware Configuration
Automatic Power-Save Mode When LRCK And BCK Are Deactivated
1.8-V or 3.3-V Fail-Safe LVCMOS Digital Inputs
Single Supply Operation:
3.3-V Analog, 1.8-V or 3.3-V Digital
Integrated Power-On Reset
Small 28-pin TSSOP Package

2 Applications

A/V Receivers
DVD, BD Players
HDTV Receivers
Applications Requiring 2-V_RMS Audio Output

3 Description

The PCM514x devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM514x uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Members of the PCM514x family integrate a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators, and other differentiating features to their products.

The PCM514x provides 2.1-V_RMS ground centered outputs, allowing designers to eliminate DC-blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ, allowing the PCM514x to drive up to 10 products in parallel, such as LCD TV, DVDR, and AV receivers.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I²S connection and reducing system EMI.

Device Information

DEVICE NAME	PACKAGE	BODY SIZE (NOM)
PCM5141	TSSOP (28)	9.70 mm × 4.40 mm
PCM5142	TSSOP (28)	9.70 mm × 4.40 mm

Simplified System Diagram

PCM5141 PCM5142 pcm1865_pcm514x_tpa3130_tpa6120a2_sysdiag.gif

4 Revision History

Changes from A Revision (September 2012) to B Revision

Deleted Internal Pop-Free Control For Sample-Rate Changes Or Clock Halts, ... With Popless OperationGo
Changed Accepts 16-, 24-, And 32-Bit Audio Data to Accepts 16-, 20-, 24-, And 32-Bit Audio DataGo
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
Clarified Pin Functions table.Go
Changed Operating temperature to Operating junction temperature in Absolute Maximum RatingsGo
Deleted redundant PLL specification in Recommended Operating Conditions Go
Deleted Intelligent clock error... and ...for pop-free performance in the Overview section.Go
Added note on instruction cycles to PCM512x Audio Processing.Go
Deleted text The Graphical Development Environment consists of number of Hybrid Flows that can be downloaded to the device and run on the miniDSP. From: Software Go
Added note on instruction cycles in Fixed Audio Processing Flow (Program 5).Go
Changed Ouptut to OutputGo
Deleted VREF mode provides 2.1V_rms full-scale output at both AVDD levels.Go
Clarified clock generation explanation in Reset and System Clock FunctionsGo
Clarified external SCK discussion in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM).Go
Deleted The PCM514x disables the internal PLL when an external SCK is supplied.Go

5 Device Comparison

Table 1. Differences Between PCM514x Devices

PART NUMBER	DYNAMIC RANGE	SNR	THD
PCM5142A	112 dB	112 dB	–93 dB
PCM5141A	106 dB	106 dB	–92 dB

Table 2. Typical Performance (3.3-V Power Supply)

PARAMETER	PCM5142 / PCM5141
SNR	112 / 106 dB
Dynamic range	112 /106 dB
THD+N at –1 dBFS	–93/ –92 dB
Full-scale single-ended output	2.1 V_RMS (GND center)
Normal 8× oversampling digital filter latency	20t_S
Low latency 8× oversampling digital filter latency	3.5t_S
Sampling frequency	8 kHz to 384 kHz
System clock multiples (f_SCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072	Up to 50 MHz

6 Pin Configuration and Functions

RHB Package
I²C Mode
(MODE1 tied to DGND and MODE2 tied to DVDD)
Top View

PCM5141 PCM5142 po_pcm512x-4x_mode1-gnd_mode2-dvdd_i2c.gif

RHB Package
Hardwired Mode
(MODE1 tied to DGND, MODE2 tied to DGND)
Top View

PCM5141 PCM5142 po_pcm512x-4x_mode1-gnd_mode2-gnd_hardwired.gif

RHB Package
SPI Mode
(MODE1 tied to DVDD)
Top View

PCM5141 PCM5142 po_pcm512x-4xmode1-dvdd_spi.gif

Table 3. Gain and Attenuation in Hardwired Mode

ATT PIN CONDITION (ATT2 : ATT1 : ATT0)	GAIN AND ATTENUATION LEVEL
( 0 0 0 )	0 dB
( 0 0 1 )	3 dB
( 0 1 0 )	6 dB
( 0 1 1 )	9 dB
( 1 0 0 )	12 dB
( 1 0 1 )	15 dB
( 1 1 0 )	–6 dB
( 1 1 1 )	–3 dB

6.1 Pin Functions

PIN				I/O	DESCRIPTION
NAME	MODE, NO.
NAME	I²C	SPI	HW
CPVDD	1	1	1	-	Charge pump power supply, 3.3 V
CAPP	2	2	2	O	Charge pump flying capacitor terminal for positive rail
CPGND	3	3	3	-	Charge pump ground
CAPM	4	4	4	O	Charge pump flying capacitor terminal for negative rail
VNEG	5	5	5	O	Negative charge pump rail terminal for decoupling, –3.3 V
OUTL	6	6	6	O	Analog output from DAC left channel
OUTR	7	7	7	O	Analog output from DAC right channel
AVDD	8	8	8	-	Analog power supply, 3.3 V
AGND	9	9	9	-	Analog ground
VCOM	10	10	–	O	I²C, SPI	VCOM output (optional mode selected by register; default setting is VREF mode.) When in VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to GND is required.
DEMP	–	–	10	I	HW	DEMP: De-emphasis control for 44.1-kHz sampling rate: Off (Low) / On (High)
SDA	11	–	–	I/O	I²C	Data for I²C⁽¹⁾⁽²⁾
MOSI	–	11	–	I	SPI	Input data for SPI⁽²⁾
ATT2	–	–	11	I	HW	Digital gain and attenuation control pin
SCL	12	–	–	I	I²C	Input clock for I²C⁽²⁾
MC	–	12	–		SPI	Input clock for SPI⁽²⁾
ATT1	–	–	12		HW	Digital gain and attenuation control pin
GPIO5	13	13	–	I/O	I²C, SPI	General purpose digital input and output port ⁽³⁾
ATT0	–	–	13	I/O	HW	Digital gain and attenuation control pin
GPIO4	14	14	–	I/O	I²C, SPI	General purpose digital input and output port ⁽³⁾
MAST	–	–	14	I/O	HW	I²S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK inputs
GPIO3	15	15	–	I/O	I²C, SPI	General purpose digital input and output port ⁽³⁾
AGNS	–	–	15	I/O	HW	Analog gain selector : 0-dB 2-V_RMS output (Low), –6-dB 1-V_RMS output (High)
ADR2	16	–	–	I/O	I²C	2nd LSB address select bit for I²C
GPIO2	–	16	–	I/O	SPI	General purpose digital input and output port
DOUT	–	–	16	O	HW	General Purpose Output (Low level)
MODE1	17	17	17	I		Mode control selection pin ⁽²⁾ MODE1 = Low, MODE2 = Low : Hardwired mode MODE1 = Low, MODE2 = High: I²C mode MODE1 = High: SPI mode
MODE2	18	–	18		I²C, HW	MODE2
MS	–	18	–	I	SPI	MS pin (chip select for SPI)
GPIO6	19	19	–	I/O	I²C, SPI	General purpose digital input and output port
FLT	–	–	19	I	HW	Filter select : Normal latency (Low) / Low latency (High)
SCK	20	20	20	I	System clock input⁽²⁾
BCK	21	21	21	I/O	Audio data bit clock input (slave) or output (master)⁽²⁾
DIN	22	22	22	I	Audio data input⁽²⁾
LRCK	23	23	23	I/O	Audio data word clock input (slave) or output (master)⁽²⁾
ADR1	24	–	–	I/O	I²C	LSB address select bit for I²C
MISO (GPIO1)	–	24	–		SPI	Primary output data for SPI readback. Secondary; general purpose digital input/output port controlled by register
FMT	–	–	24		HW	Audio format selection : I²S (Low) / Left justified (High)
XSMT	25	25	25	I	Soft mute control Soft mute⁽²⁾ (Low) / soft un-mute (High)
LDOO	26	26	26	-	Internal logic supply rail terminal for decoupling, 1.8 V
DGND	27	27	27	-	Digital ground
DVDD	28	28	28	-	Digital power supply, 3.3 V or 1.8 V

(1) Open-drain configuration in out mode.

(2) Failsafe LVCMOS Schmitt trigger input.

(3) Internal Pulldown

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage	AVDD, CPVDD, DVDD	–0.3	3.9	V
Supply voltage	LDO with DVDD at 1.8 V	–0.3	2.25	V
Digital input voltage	DVDD at 1.8 V	–0.3	2.25	V
Digital input voltage	DVDD at 3.3 V	–0.3	3.9	V
Analog input voltage		–0.3	3.9	V
Operating junction temperature, T_J		–40	130	°C
Storage temperature, T_stg		–65	150	°C

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
A_VDD	Analog power supply voltage	Referenced to AGND⁽¹⁾	VCOM mode	3	3.3	3.46	V
A_VDD	Analog power supply voltage	Referenced to AGND⁽¹⁾	VREF mode	3.2	3.3	3.46	V
D_VDD	Digital power supply voltage	Referenced to DGND⁽¹⁾	1.8 V DVDD	1.65	1.8	1.95	V
D_VDD	Digital power supply voltage	Referenced to DGND⁽¹⁾	3.3 V DVDD	3.1	3.3	3.46	V
CPVDD	Charge pump supply voltage	Referenced to CPGND⁽¹⁾		3.1	3.3	3.46	V
MCLK	Master clock frequency					50	MHz
LOL, LOR	Stereo line output load resistance			1	10		kΩ
C_LOUT	Digital output load capacitance				10		pF
T_J	Operating junction temperature			–40		130	°C

(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2-V maximum, for any combination of ground signals.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		PCM512x	UNIT
		RHB (TSSOP)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	72.2	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	17.5	°C/W
R_θJB	Junction-to-board thermal resistance	35.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	34.5	°C/W

(1) For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

T_A = 25°C, AV_DD = CPV_DD = DV_DD = 3.3 V, f_S = 48 kHz, system clock = 512 f_S and 24-bit data (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution		16	24	32	Bits
DIGITAL INPUT/OUTPUT
Logic Family: 3.3-V LVCMOS Compatible
V_IH	Input logic level, high		0.7 × DV_DD			V
V_IL	Input logic level, low				0.3 × DV_DD	V
I_IH	Input logic current, high	V_IN = V_DD			10	µA
I_IL	Input logic current, low	V_IN = 0 V			–10	µA
V_OH	Output logic level, high	I_OH = –4 mA	0.8 × DV_DD			V
V_OL	Output logic level, low	I_OL = 4 mA			0.22 × DV_DD	V
Logic Family 1.8-V LVCMOS Compatible
V_IH	Input logic level, high		0.7 × DV_DD			V
V_IL	Input logic level, low				0.3 × DV_DD	V
I_IH	Input logic current, high	V_IN = V_DD			10	µA
I_IL	Input logic current, low	V_IN = 0 V			–10	µA
V_OH	Output logic level, high	I_OH = –2 mA	0.8 × DV_DD			V
V_OL	Output logic level, low	I_OL = 2 mA			0.22 × DV_DD	V
DYNAMIC PERFORMANCE (PCM MODE)⁽¹⁾⁽²⁾
	THD+N at –1 dB⁽²⁾	f_S = 48 kHz		–93	–83	dB
		f_S = 96 kHz		–93
		f_S = 192 kHz		–93
	Dynamic range⁽²⁾	EIAJ, A-weighted, f_S = 48 kHz	108	112		dB
		EIAJ, A-weighted, f_S = 96 kHz		112
		EIAJ, A-weighted, f_S = 192 kHz		112
	Signal-to-noise ratio⁽²⁾	EIAJ, A-weighted, f_S = 48 kHz		112		dB
		EIAJ, A-weighted, f_S = 96 kHz		112
		EIAJ, A-weighted, f_S = 192 kHz		112
	Signal-to-noise ratio with analog mute⁽²⁾⁽³⁾	EIAJ, A-weighted, f_S = 48 kHz	113	123		dB
		EIAJ, A-weighted, f_S = 96 kHz	113	123
		EIAJ, A-weighted, f_S = 192 kHz	113	123
	Channel separation	f_S = 48 kHz	100 / 95	109 / 103		dB
		f_S = 96 kHz	100 / 95	109 / 103
		f_S = 192 kHz	100 / 95	109 / 103
ANALOG OUTPUT
	Single-ended output voltage			2.1		V_RMS
	Gain error		–6	±2.0	6	% of FSR
	Gain mismatch, channel-to-channel		–6	±0.5	6	% of FSR
	Load impedance		5			kΩ
FILTER CHARACTERISTICS–1: NORMAL (8x)
	Pass band				0.45 × f_S	kHz
	Stop band		0.55 × f_S			kHz
	Stop band attenuation		–60			dB
	Pass-band ripple				±0.02	dB
	Delay time			20 × t_S		s
FILTER CHARACTERISTICS–2: LOW LATENCY (8x)
	Pass band				0.47 × f_S	kHz
	Stop band		0.55 × f_S			kHz
	Stop band attenuation		–52			dB
	Pass-band ripple				±0.0001	dB
	Delay time			3.5 × t_S		s
FILTER CHARACTERISTICS–3: ASYMMETRIC FIR (8x)
	Pass band				0.4 × f_S	kHz
	Stop band		0.72 × f_S			kHz
	Stop band attenuation		–52			dB
	Pass-band ripple				±0.05	dB
	Delay time			1.2 × t_S		s
FILTER CHARACTERISTICS–4: HIGH-ATTENUATION (8x)
	Pass band				0.45 × f_S	kHz
	Stop band		0.45 × f_S			kHz
	Stop band attenuation			–100		dB
	Pass-band ripple				±0.0005	dB
	Delay time			33.7 × t_S		s
POWER SUPPLY REQUIREMENTS
DV_DD	Digital supply voltage	Target DV_DD = 1.8 V	1.65	1.8	1.95	VDC
DV_DD	Digital supply voltage	Target DV_DD = 3.3 V	3	3.3	3.6	VDC
AV_DD	Analog supply voltage		3	3.3	3.6	VDC
CPV_DD	Charge-pump supply voltage		3	3.3	3.6	VDC
I_DD	DV_DD supply current at 1.8 V	f_S = 48 kHz, input is bipolar zero data		11	14	mA
		f_S = 96 kHz, input is bipolar zero data		12
		f_S = 192 kHz, input is bipolar zero data		14
I_DD	DV_DD supply current at 1.8 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		11	14	mA
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		12
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		14
I_DD	DV_DD supply current at 1.8 V⁽⁴⁾	f_S = N/A, power-down mode		0.3	0.6	mA
I_DD	DV_DD supply current at 3.3 V	f_S = 48 kHz, input is bipolar zero data		12	15	mA
		f_S = 96 kHz, input is bipolar zero data		13
		f_S = 192 kHz, input is bipolar zero data		15
I_DD	DV_DD supply current at 3.3 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		12	15	mA
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		13
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		15
I_DD	DV_DD supply current at 3.3 V⁽⁴⁾	f_S = N/A, power-down mode		0.5	0.8	mA
I_CC	AV_DD + CPV_DD supply current	f_S = 48 kHz, input is bipolar zero data		11	16	mA
		f_S = 96 kHz, input is bipolar zero data		11
		f_S = 192 kHz, input is bipolar zero data		11
I_CC	AV_DD + CPV_DD supply current	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		24	32	mA
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		24
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		24
I_CC	AV_DD + CPV_DD supply current⁽⁴⁾	f_S = N/A, power-down mode		0.2	0.4	mA
	Power dissipation, DV_DD = 1.8 V	f_S = 48 kHz, input is bipolar zero data		59.4	78	mW
		f_S = 96 kHz, input is bipolar zero data		61.2
		f_S = 192 kHz, input is bipolar zero data		64.8
	Power dissipation, DV_DD = 1.8 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		99	130.8	mW
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		100.8
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		104.4
	Power dissipation, DV_DD = 1.8 V⁽⁴⁾	f_S = N/A, power-down mode		1.2		mW
	Power dissipation, DV_DD = 3.3 V	f_S = 48 kHz, input is bipolar zero data		79.2	103	mW
		f_S = 96 kHz, input is bipolar zero data		82.5
		f_S = 192 kHz, input is bipolar zero data		89.1
	Power dissipation, DV_DD = 3.3 V	f_S = 48 kHz, input is 1 kHz – 1 dBFS data		118.8	155	mW
		f_S = 96 kHz, input is 1 kHz – 1 dBFS data		122.1
		f_S = 192 kHz, input is 1 kHz – 1 dBFS data		128.7
	Power dissipation, DV_DD = 3.3 V⁽⁴⁾	f_S = N/A, power-down mode		2.3	4	mW

(1) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.

(2) Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see Recommended Output Filter for the PCM514x).

(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ

(4) Power-down mode, with LRCK, BCK, and SCK halted at low level.

7.6 Timing Requirements: SCK Input

Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise.

			MIN	MAX	UNIT
t_SCY	System clock pulse cycle time		20	1000	ns
t_SCKH	System clock pulse width, high	DVDD = 1.8 V	8		ns
t_SCKH	System clock pulse width, high	DVDD = 3.3 V	9		ns
t_SCKL	System clock pulse width, low	DVDD = 1.8 V	8		ns
t_SCKL	System clock pulse width, low	DVDD = 3.3 V	9		ns

7.7 Timing Requirements: PCM Audio Data

		MIN	MAX	UNIT
t_BCY	BCK Pulse Cycle Time	40		ns
t_BCL	BCK Pulse Width LOW	16		ns
t_BCH	BCK Pulse Width HIGH	16		ns
t_BL	BCK Rising Edge to LRCK Edge	8		ns
t_BCK	BCK frequency at DVDD = 3.3 V		24.576	MHz
t_BCK(1.8V)	BCK frequency at DVDD = 1.8 V		12.288	MHz
t_LB	LRCK Edge to BCK Rising Edge	8		ns
t_DS	DATA Set Up Time	8		ns
t_DH	DATA Hold Time	8		ns
t_DOD	DATA delay time from BCK falling edge		15	ns

7.7.1 Timing Requirements: I²S Master

		MIN	MAX	UNIT
t_BCY	BCK Pulse Cycle Time	40		ns
t_BCL	BCK Pulse Width LOW	16		ns
t_BCH	BCK Pulse Width HIGH	16		ns
t_BCK	BCK frequency at DVDD = 3.3 V		24.576	MHz
t_BCK(1.8V)	BCK frequency at DVDD = 1.8 V		12.288	MHz
t_LRD	LRCKx delay time from BCKx falling edge	–10	20	ns
t_DS	DATA Set Up Time	8		ns
t_DH	DATA Hold Time	8		ns
t_DOD	DATA delay time from BCK falling edge at DVDD = 3.3 V		15	ns
t_DOD(1.8V)	DATA delay time from BCK falling edge at DVDD = 1.8 V		20	ns

7.8 Timing Requirements: XSMT

		MIN	NOM	MAX	UNIT
t_r	Rise time			20	ns
t_f	Fall time			20	ns

7.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
DATA FORMAT (PCM MODE)
	Audio data interface format		I²S, left-justified, right-justified, and TDM
	Audio data bit length		16, 20, 24, 32-bit acceptable
	Audio data format		MSB first, twos-complement
f_S	Sampling frequency⁽¹⁾		8	384	kHz
CLOCKS
	System clock frequency		64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 f_SCK, up to 50 Mhz
	PLL input frequency ⁽²⁾	Clock divider uses fractional divide D > 0, P=1	6.7	20	MHz
	PLL input frequency ⁽²⁾	Clock divider uses integer divide D = 0, P=1	1	20	MHz

(1) One sample time is defined as the reciprocal of the sampling frequency. 1 × t_S = 1 / f_S

(2) With the appropriate P coefficient setting, the PLL accepts up to 50 MHz. This clock is then divided to meet the ≤ 20-MHz requirement. See PLL Calculation.

PCM5141 PCM5142 f_pcm51xx_td_sck_req.gif

Figure 1. Timing Requirements for SCK Input

PCM5141 PCM5142 f_pcm512x4x_td_pcm_aud_slv.gif

Figure 2. PCM514x Serial Audio Timing - Slave

PCM5141 PCM5142 f_pcm512x4x_td_pcm_aud_mstr.gif

Figure 3. PCM514x Serial Audio Timing - I²S Master

PCM5141 PCM5142 f_pcm51xx_td_xsmt_soft_mute.gif

Figure 4. XSMT Timing for Soft Mute and Soft Un-Mute

7.10 Typical Characteristics

Consumer grade (non-Q1) devices are specified for T_A = 25°C, AV_DD = CPV_DD = DV_DD = 3.3 V, f_S = 48 kHz, system clock = 512 f_S and 24-bit data (unless otherwise noted).

PCM5141 PCM5142 thd_n_input_level_5101.gif

Figure 5. PCM5141 THD+N vs Input Level

Figure 7. PCM5141 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 20 kHz

Figure 9. PCM5141 FFT Plot at Bipolar Zero Data (BPZ)

Figure 11. PCM5141 FFT Plot at BPZ With Analog Mute (AMUTE)

PCM5141 PCM5142 fft_-60_sub_300kHz_5101.gif

Figure 13. PCM5141 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 300 kHz

PCM5141 PCM5142 thd_n_input_level_5102.gif

Figure 6. PCM5142 THD+N vs Input Level

Figure 8. PCM5142 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 20 kHz

Figure 10. PCM5142 FFT Plot at BPZ

Figure 12. PCM5142 FFT Plot at BPZ With Analog Mute (AMUTE)

PCM5141 PCM5142 fft_-60_sub_300kHz_5102.gif

Figure 14. PCM5142 FFT Plot Using a 1-kHz Tone
(–60 dBFS) from DC to 300 kHz