SLASE12A July   2014  – October 2014 PCM5242

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified System Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
    1. 6.1 Control Mode Effect On Pin Assignments
    2. 6.2 Pin Assignments
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Requirements: SCK Input
    8. 7.8 Timing Requirements: PCM Audio Data
    9. 7.9 Timing Requirements: XSMT
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Terminology
    4. 8.4 Audio Data Interface
      1. 8.4.1 Audio Serial Interface
      2. 8.4.2 PCM Audio Data Formats
      3. 8.4.3 Zero Data Detect
    5. 8.5 XSMT Pin (Soft Mute / Soft Un-Mute)
    6. 8.6 Audio Processing
      1. 8.6.1 PCM5242 Audio Processing Options
        1. 8.6.1.1 Overview
        2. 8.6.1.2 miniDSP Instruction Register
        3. 8.6.1.3 Digital Output
        4. 8.6.1.4 Software
      2. 8.6.2 Interpolation Filter
      3. 8.6.3 Fixed Audio Processing Flow (Program 5)
        1. 8.6.3.1 Processing Blocks - Detailed Descriptions
        2. 8.6.3.2 Biquad Section
        3. 8.6.3.3 Dynamic Range Compression
        4. 8.6.3.4 Stereo Mixer
        5. 8.6.3.5 Stereo Multiplexer
        6. 8.6.3.6 Mono Mixer
        7. 8.6.3.7 Master Volume Control
        8. 8.6.3.8 Miscellaneous Coefficients
    7. 8.7 DAC and Differential Analog Outputs
      1. 8.7.1 Analog Outputs
      2. 8.7.2 Choosing Between VREF and VCOM Modes
        1. 8.7.2.1 Voltage Reference and Output Levels
        2. 8.7.2.2 Mode Switching Sequence, From VREF Mode to VCOM Mode
      3. 8.7.3 Digital Volume Control
        1. 8.7.3.1 Emergency Ramp Down
      4. 8.7.4 Analog Gain Control
    8. 8.8 Reset and System Clock Functions
      1. 8.8.1 Clocking Overview
      2. 8.8.2 Clock Slave Mode With Master Clock (SCK) Input (4 Wire I2S)
      3. 8.8.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
      4. 8.8.4 Clock Generation Using The PLL
      5. 8.8.5 PLL Calculation
        1. 8.8.5.1 Examples:
          1. 8.8.5.1.1 Recommended PLL settings
      6. 8.8.6 Clock Master Mode from Audio Rate Master Clock
      7. 8.8.7 Clock Master from a Non-Audio Rate Master Clock
    9. 8.9 Device Functional Modes
      1. 8.9.1 Choosing A Control Mode
        1. 8.9.1.1 Software Control
          1. 8.9.1.1.1 SPI Interface
            1. 8.9.1.1.1.1 Register Read/Write Operation
          2. 8.9.1.1.2 I2C Interface
            1. 8.9.1.1.2.1 Slave Address
            2. 8.9.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.9.1.1.2.3 Packet Protocol
            4. 8.9.1.1.2.4 Write Register
            5. 8.9.1.1.2.5 Read Register
            6. 8.9.1.1.2.6 Timing Characteristics
      2. 8.9.2 Choosing Between VREF and VCOM Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Fidelity Smartphone Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Initialization Script
        3. 9.2.1.3 Application Performance Plot
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 Planned Shutdown
      2. 10.2.2 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection mode (supported only when DVDD = 3.3V)
    4. 10.4 PCM5242 Power Modes
      1. 10.4.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 10.4.2 Power Save Modes
      3. 10.4.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Programming and Registers Reference
    1. 12.1 Coefficient Data Formats
    2. 12.2 PCM5242 Register Map
      1. 12.2.1 Detailed Register Descriptions
        1. 12.2.1.1 Register Map Summary
          1. 12.2.1.1.1 Register Map Summary
        2. 12.2.1.2 Page 0 Registers
          1. 12.2.1.2.1  Page 0 / Register 1
          2. 12.2.1.2.2  Page 0 / Register 2
          3. 12.2.1.2.3  Page 0 / Register 3
          4. 12.2.1.2.4  Page 0 / Register 4
          5. 12.2.1.2.5  Page 0 / Register 6
          6. 12.2.1.2.6  Page 0 / Register 7
          7. 12.2.1.2.7  Page 0 / Register 8
          8. 12.2.1.2.8  Page 0 / Register 9
          9. 12.2.1.2.9  Page 0 / Register 10
          10. 12.2.1.2.10 Page 0 / Register 12
          11. 12.2.1.2.11 Page 0 / Register 13
          12. 12.2.1.2.12 Page 0 / Register 14
          13. 12.2.1.2.13 Page 0 / Register 18
          14. 12.2.1.2.14 Page 0 / Register 19
          15. 12.2.1.2.15 Page 0 / Register 20
          16. 12.2.1.2.16 Page 0 / Register 21
          17. 12.2.1.2.17 Page 0 / Register 22
          18. 12.2.1.2.18 Page 0 / Register 23
          19. 12.2.1.2.19 Page 0 / Register 24
          20. 12.2.1.2.20 Page 0 / Register 27
          21. 12.2.1.2.21 Page 0 / Register 28
          22. 12.2.1.2.22 Page 0 / Register 29
          23. 12.2.1.2.23 Page 0 / Register 30
          24. 12.2.1.2.24 Page 0 / Register 32
          25. 12.2.1.2.25 Page 0 / Register 33
          26. 12.2.1.2.26 Page 0 / Register 34
          27. 12.2.1.2.27 Page 0 / Register 35
          28. 12.2.1.2.28 Page 0 / Register 36
          29. 12.2.1.2.29 Page 0 / Register 37
          30. 12.2.1.2.30 Page 0 / Register 40
          31. 12.2.1.2.31 Page 0 / Register 41
          32. 12.2.1.2.32 Page 0 / Register 42
          33. 12.2.1.2.33 Page 0 / Register 43
          34. 12.2.1.2.34 Page 0 / Register 44
          35. 12.2.1.2.35 Page 0 / Register 59
          36. 12.2.1.2.36 Page 0 / Register 60
          37. 12.2.1.2.37 Page 0 / Register 61
          38. 12.2.1.2.38 Page 0 / Register 62
          39. 12.2.1.2.39 Page 0 / Register 63
          40. 12.2.1.2.40 Page 0 / Register 64
          41. 12.2.1.2.41 Page 0 / Register 65
          42. 12.2.1.2.42 Page 0 / Register 80
          43. 12.2.1.2.43 Page 0 / Register 81
          44. 12.2.1.2.44 Page 0 / Register 82
          45. 12.2.1.2.45 Page 0 / Register 83
          46. 12.2.1.2.46 Page 0 / Register 84
          47. 12.2.1.2.47 Page 0 / Register 85
          48. 12.2.1.2.48 Page 0 / Register 86
          49. 12.2.1.2.49 Page 0 / Register 87
          50. 12.2.1.2.50 Page 0 / Register 90
          51. 12.2.1.2.51 Page 0 / Register 91
          52. 12.2.1.2.52 Page 0 / Register 92
          53. 12.2.1.2.53 Page 0 / Register 93
          54. 12.2.1.2.54 Page 0 / Register 94
          55. 12.2.1.2.55 Page 0 / Register 95
          56. 12.2.1.2.56 Page 0 / Register 108
          57. 12.2.1.2.57 Page 0 / Register 109
          58. 12.2.1.2.58 Page 0 / Register 114
          59. 12.2.1.2.59 Page 0 / Register 115
          60. 12.2.1.2.60 Page 0 / Register 118
          61. 12.2.1.2.61 Page 0 / Register 119
          62. 12.2.1.2.62 Page 0 / Register 120
          63. 12.2.1.2.63 Page 0 / Register 121
          64. 12.2.1.2.64 Page 0 / Register 122
          65. 12.2.1.2.65 Page 0 / Register 123
          66. 12.2.1.2.66 Page 0 / Register 124
          67. 12.2.1.2.67 Page 0 / Register 125
        3. 12.2.1.3 Page 1 Registers
          1. 12.2.1.3.1 Page 1 / Register 1
          2. 12.2.1.3.2 Page 1 / Register 2
          3. 12.2.1.3.3 Page 1 / Register 5
          4. 12.2.1.3.4 Page 1 / Register 6
          5. 12.2.1.3.5 Page 1 / Register 7
          6. 12.2.1.3.6 Page 1 / Register 8
          7. 12.2.1.3.7 Page 1 / Register 9
        4. 12.2.1.4 Page 44 Registers
          1. 12.2.1.4.1 Page 44 / Register 1
        5. 12.2.1.5 Page 253 Registers
          1. 12.2.1.5.1 Page 253 / Register 63
          2. 12.2.1.5.2 Page 253 / Register 64
      2. 12.2.2 PLL Tables for Software Controlled Devices
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • The PCM5242 is a simple device to layout. Most engineers use a shared common ground for the entire device. GND can be consider AGND and DGND connected.
  • Good system partitioning should keep digital clock and interface traces away from the differential analog outputs for highest analog performance. This reduces any high speed clock return currents influencing the analog outputs.
  • Power supply and charge pump decoupling capacitors should be placed as close as possible to the device.
  • The thermal pad on the underside of the package should be connected to GND.
  • The top layer should be used for routing signals, whilst the bottom layer can be used for GND.

layout_slase12.gifFigure 88. PCM5252 Layout Example