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  • PCM5252 Purepath™ Smart Amp 4.2-VRMS DirectPath, 114-dB Audio Stereo Differential-Output DAC with 32-bit, 384-kHz PCM Interface

    • SLASE63 November   2014 PCM5252

      PRODUCTION DATA.  

  • CONTENTS
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  • PCM5252 Purepath™ Smart Amp 4.2-VRMS DirectPath, 114-dB Audio Stereo Differential-Output DAC with 32-bit, 384-kHz PCM Interface
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Control Mode Effect On Pin Assignments
    2. 6.2 Pin Assignments
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics
    7. 7.7  Timing Requirements: SCK Input
    8. 7.8  Timing Requirements: PCM Audio Data
    9. 7.9  Timing Requirements: I2S Master, See
    10. 7.10 Timing Requirements: XSMT
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1  PCM5252 Audio Processing Options
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 miniDSP Instruction Register
          3. 8.3.4.1.3 Digital Output
          4. 8.3.4.1.4 Software
        2. 8.3.4.2  Interpolation Filter
        3. 8.3.4.3  Overview
        4. 8.3.4.4  Smart SOA
        5. 8.3.4.5  Smart BASS
        6. 8.3.4.6  Smart Protection
        7. 8.3.4.7  Implementing a Real World Design
        8. 8.3.4.8  Digital Output
        9. 8.3.4.9  Software
        10. 8.3.4.10 Process Flow
      5. 8.3.5 DAC and Differential Analog Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Choosing Between VREF and VCOM Modes
          1. 8.3.5.2.1 Voltage Reference and Output Levels
          2. 8.3.5.2.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        3. 8.3.5.3 Digital Volume Control
          1. 8.3.5.3.1 Emergency Ramp-Down
        4. 8.3.5.4 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Fidelity Smartphone Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Initialization Script
        3. 9.2.1.3 Application Performance Plot
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM5252 Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
        1. 13.2.2 PLL Tables for Software Controlled Devices
      2. 10.5.2 Power Save Modes
        1. 13.2.1.3 Page 1 Registers
          1. 13.2.1.3.1 Page 1 / Register 1
          2. 13.2.1.3.2 Page 1 / Register 2
          3. 13.2.1.3.3 Page 1 / Register 5
          4. 13.2.1.3.4 Page 1 / Register 6
          5. 13.2.1.3.5 Page 1 / Register 7
          6. 13.2.1.3.6 Page 1 / Register 8
          7. 13.2.1.3.7 Page 1 / Register 9
        2. 13.2.1.4 Page 44 Registers
          1. 13.2.1.4.1 Page 44 / Register 1
        3. 13.2.1.5 Page 253 Registers
          1. 13.2.1.5.1 Page 253 / Register 63
          2. 13.2.1.5.2 Page 253 / Register 64
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 13.2.1.2.19 Page 0 / Register 24
      2. 13.2.1.2.20 Page 0 / Register 27
      3. 13.2.1.2.21 Page 0 / Register 28
      4. 13.2.1.2.22 Page 0 / Register 29
      5. 13.2.1.2.23 Page 0 / Register 30
      6. 13.2.1.2.24 Page 0 / Register 32
      7. 13.2.1.2.25 Page 0 / Register 33
      8. 13.2.1.2.26 Page 0 / Register 34
      9. 13.2.1.2.27 Page 0 / Register 35
      10. 13.2.1.2.28 Page 0 / Register 36
      11. 13.2.1.2.29 Page 0 / Register 37
      12. 13.2.1.2.30 Page 0 / Register 40
      13. 13.2.1.2.31 Page 0 / Register 41
      14. 13.2.1.2.32 Page 0 / Register 42
      15. 13.2.1.2.33 Page 0 / Register 43
      16. 13.2.1.2.34 Page 0 / Register 44
      17. 13.2.1.2.35 Page 0 / Register 59
      18. 13.2.1.2.36 Page 0 / Register 60
      19. 13.2.1.2.37 Page 0 / Register 61
      20. 13.2.1.2.38 Page 0 / Register 62
      21. 13.2.1.2.39 Page 0 / Register 63
      22. 13.2.1.2.40 Page 0 / Register 64
      23. 13.2.1.2.41 Page 0 / Register 65
      24. 13.2.1.2.42 Page 0 / Register 80
      25. 13.2.1.2.43 Page 0 / Register 81
      26. 13.2.1.2.44 Page 0 / Register 82
      27. 13.2.1.2.45 Page 0 / Register 83
      28. 13.2.1.2.46 Page 0 / Register 84
      29. 13.2.1.2.47 Page 0 / Register 85
      30. 13.2.1.2.48 Page 0 / Register 86
      31. 13.2.1.2.49 Page 0 / Register 87
      32. 13.2.1.2.50 Page 0 / Register 90
      33. 13.2.1.2.51 Page 0 / Register 91
      34. 13.2.1.2.52 Page 0 / Register 92
      35. 13.2.1.2.53 Page 0 / Register 93
      36. 13.2.1.2.54 Page 0 / Register 94
      37. 13.2.1.2.55 Page 0 / Register 95
      38. 13.2.1.2.56 Page 0 / Register 108
      39. 13.2.1.2.57 Page 0 / Register 109
      40. 13.2.1.2.58 Page 0 / Register 114
      41. 13.2.1.2.59 Page 0 / Register 115
      42. 13.2.1.2.60 Page 0 / Register 118
      43. 13.2.1.2.61 Page 0 / Register 119
      44. 13.2.1.2.62 Page 0 / Register 120
      45. 13.2.1.2.63 Page 0 / Register 121
      46. 13.2.1.2.64 Page 0 / Register 122
      47. 13.2.1.2.65 Page 0 / Register 123
      48. 13.2.1.2.66 Page 0 / Register 124
      49. 13.2.1.2.67 Page 0 / Register 125
    2. 11.2 Layout Example
  12. 12Programming
    1. 12.1 Coefficient Data Formats
    2. 12.2 Power Down and Reset Behavior
  13. 13Register Maps
    1. 13.1 PCM5252 Register Map
      1. 13.1.1 Detailed Register Descriptions
        1. 13.1.1.1 Register Map Summary
        2. 13.1.1.2 Page 0 Registers
        3. 13.1.1.3 Page 1 Registers
        4. 13.1.1.4 Page 44 Registers
        5. 13.1.1.5 Page 253 Registers
      2. 13.1.2 PLL Tables for Software Controlled Devices
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  15. 15Mechanical, Packaging, and Orderable Information
  16. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  17. 15Mechanical, Packaging, and Orderable Information
  18. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RHB|32
    • MPQF130D
Thermal pad, mechanical data (Package|Pins)
  • RHB|32
    • QFND029X
Orderable Information
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DATA SHEET

PCM5252 Purepath™ Smart Amp 4.2-VRMS DirectPath, 114-dB Audio Stereo Differential-Output DAC with 32-bit, 384-kHz PCM Interface

1 Features

  • Differential DirectPath™ Ground Biased Outputs
  • Smart Amplifier Technology
  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • No DC Blocking Capacitors Required
  • Integrated Negative Charge Pump
  • Intelligent Muting System; Soft Up or Down Ramp and Analog Mute for 120-dB Mute SNR
  • Integrated High-Performance Audio PLL With BCK Reference to Generate SCK Internally
  • Accepts 16-Bit, 24-Bit, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • SPI or I2C Control
  • Hardware Configuration
  • Automatic Power-Save Mode When LRCK And BCK Are Deactivated
  • 1.8-V or 3.3-V Failsafe LVCMOS Digital Inputs
  • Single Supply Operation:
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Integrated Power-On Reset
  • Small 32-pin VQFN Package

2 Applications

  • HiFi Smartphone
  • A/V Receivers
  • DVD, BD Players
  • HDTV Receivers

3 Description

The PCM5252 is a monolithic CMOS integrated circuit that includes a stereo digital-to-analog converter and additional support circuitry in a small QFN package. The PCM5252 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

The PCM5252 integrates a fully programmable miniDSP core, allowing developers to integrate filters, dynamic range controls, custom interpolators, and other differentiating features to their products.

The PCM5252 integrates ROM components of TI's PurePath™ Smart Amp technology, which allows speakers to be driven with more peak power than their average-power rating, without damage to the speaker by voice coil over excursion or thermal overload.

The PCM5252 provides 4.2-VRMS ground-centered differential outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Block diagrams for the can be found at Functional Block Diagram.

Device Information(1)

PART NAME PACKAGE BODY SIZE (NOM)
PCM5252 VQFN (32) 5.00mm × 5.00mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified System Diagram

PCM5252 Sim_sys_dia_pcm5252_slase63.gif

4 Revision History

DATE REVISION NOTES
November 2014 * Initial release.

5 Device Comparison

Table 1. Typical Performance (3.3-V Power Supply)

PARAMETER PCM5252
SNR 114 dB
Dynamic range 114 dB
THD+N at –1 dBFS -93 dB
Full-scale single-ended output 4.2 VRMS (GND center)
Normal 8× oversampling digital filter latency 20/fS
Low latency 8× oversampling digital filter latency 3.5/fS
Sampling frequency 8 kHz to 384 kHz
System clock multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072 Up to 50 MHz

6 Pin Configuration and Functions

6.1 Control Mode Effect On Pin Assignments

The PCM5252 supports control from I2C, SPI and Hardware Modes (referred to as HW mode). Selection of modes is done using MODE1 and MODE2 pins. (See the PCM5252 Pin Functions table.

SPI Mode is selected by pulling MODE1 to DVDD.

I2C Mode is selected by pulling MODE1 to DGND and MODE2 to DVDD.

Hardware Control Mode is selected by pulling both MODE1 and MODE2 pins to DGND.

6.2 Pin Assignments

QFN Package
32-Pin RHB
Top View
PCM5252 po_rhb32_i2c_pcm52xx.gif Figure 1. I2C Control
QFN Package
32-Pin RHB
Top View
PCM5252 po_rhb32_spi_pcm52xx.gif Figure 2. SPI Control
QFN Package
32-Pin RHB
Top View
PCM5252 po_rhb32_hwc_pcm52xx.gif Figure 3. Hardware Control

PCM5252 Pin Functions

PIN I/O DESCRIPTION
MODE, NAME PIN
I2C SPI HW
XSMT 1 I Soft mute control(2) Soft mute (Low) / soft un-mute (High)
LDOO 2 - Internal logic supply rail pin for decoupling, 1.8V
DGND 3 - Digital ground
DVDD 4 - Digital power supply, 3.3V or 1.8V
CPVDD 5 - Charge pump power supply, 3.3V
CAPP 6 O Charge pump flying capacitor pin for positive rail
CPGND 7 - Charge pump ground
CAPM 8 O Charge pump flying capacitor pin for negative rail
VNEG 9 O Negative charge pump rail pin for decoupling, -3.3V
OUTLP 10 Positive Differential Analog output from DAC left channel
OUTLN 11 Negative Differential Analog output from DAC left channel
OUTRN 12 Negative Differential Analog output from DAC right channel
OUTRP 13 Positive Differential Analog output from DAC right channel.
AVDD 14 - Analog power supply, 3.3V
AGND 15 - Analog ground
VCOM 16 O I2C, SPI VCOM output (Optional mode selected by register; default setting is VREF mode.) When in VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to GND is required.
DEMP I HW DEMP: De-emphasis control for 44.1kHz sampling rate: Off (Low) / On (High)
SDA 17 I/O I2C Data for I2C(1)(2)
MOSI I SPI Input data for SPI(2)
ATT2 HW Digital gain and attenuation control pin
SCL 18 I I2C Input clock for I2C(2)
MC SPI Input clock for SPI(2)
ATT1 HW Digital gain and attenuation control pin
GPIO5 19 I/O I2C, SPI General purpose digital input and output port (3)
ATT0 HW Digital gain and attenuation control pin
GPIO4 20 I/O I2C, SPI General purpose digital input and output port (3)
MAST HW I2S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK inputs
GPIO3 21 I/O I2C, SPI General purpose digital input and output port (3)
AGNS HW Analog gain selector : 0dB 2VRMS output (Low), -6dB 1VRMS output (High)
ADR2 22 I/O I2C 2nd LSB address select bit for I2C(3)
GPIO2 SPI General purpose digital input and output port (3)
GPO O HW General Purpose Output (Low level)
MODE1 23 I Mode control selection pin(2)
MODE1 = Low, MODE2 = Low : Hardwired mode Reserved
MODE1 = Low, MODE2 = High: I2C mode
MODE1 = High: SPI mode
MODE2 MODE2 24 I2C, HW MODE2 (See definition in Mode 1 description)
MS I SPI MS pin (chip select for SPI)
GPIO6 25 I/O I2C, SPI General purpose digital input and output port
FLT I HW Filter select : Normal latency (Low) / Low latency (High)
SCK 26 I System clock input(2)
BCK 27 I/O Audio data bit clock input (slave) or output (master)(2)
DIN 28 I Audio data input(2)
NC 29 - No connect
30 -
LRCK 31 I/O Audio data word clock input (slave) or output (master)(2)
ADR1 32 I/O I2C LSB address select bit for I2C
MISO (GPIO1) SPI Primary output data for SPI readback. Secondary; general purpose digital input/output port controlled by register
FMT HW Audio format selection : I2S (Low) / Left justified (High)
(1) Open-drain configuration in out mode.
(2) Failsafe LVCMOS Schmitt trigger input.
(3) Internal Pulldown

Table 2. Gain and Attenuation in Hardwired Mode

ATT PIN CONDITION
(ATT2 : ATT1 : ATT0)		 GAIN AND ATTENUATION LEVEL
( 0 0 0 ) 0 dB
( 0 0 1 ) + 3 dB
( 0 1 0 ) + 6 dB
( 0 1 1 ) + 9 dB
( 1 0 0 ) + 12 dB
( 1 0 1 ) + 15 dB
( 1 1 0 ) - 6 dB
( 1 1 1 ) - 3 dB

 
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