SLASE63 November   2014 PCM5252

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Control Mode Effect On Pin Assignments
    2. 6.2 Pin Assignments
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics
    7. 7.7  Timing Requirements: SCK Input
    8. 7.8  Timing Requirements: PCM Audio Data
    9. 7.9  Timing Requirements: I2S Master, See
    10. 7.10 Timing Requirements: XSMT
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1  PCM5252 Audio Processing Options
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 miniDSP Instruction Register
          3. 8.3.4.1.3 Digital Output
          4. 8.3.4.1.4 Software
        2. 8.3.4.2  Interpolation Filter
        3. 8.3.4.3  Overview
        4. 8.3.4.4  Smart SOA
        5. 8.3.4.5  Smart BASS
        6. 8.3.4.6  Smart Protection
        7. 8.3.4.7  Implementing a Real World Design
        8. 8.3.4.8  Digital Output
        9. 8.3.4.9  Software
        10. 8.3.4.10 Process Flow
      5. 8.3.5 DAC and Differential Analog Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Choosing Between VREF and VCOM Modes
          1. 8.3.5.2.1 Voltage Reference and Output Levels
          2. 8.3.5.2.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        3. 8.3.5.3 Digital Volume Control
          1. 8.3.5.3.1 Emergency Ramp-Down
        4. 8.3.5.4 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Fidelity Smartphone Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Initialization Script
        3. 9.2.1.3 Application Performance Plot
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM5252 Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
        1. 13.2.2 PLL Tables for Software Controlled Devices
      2. 10.5.2 Power Save Modes
        1. 13.2.1.3 Page 1 Registers
          1. 13.2.1.3.1 Page 1 / Register 1
          2. 13.2.1.3.2 Page 1 / Register 2
          3. 13.2.1.3.3 Page 1 / Register 5
          4. 13.2.1.3.4 Page 1 / Register 6
          5. 13.2.1.3.5 Page 1 / Register 7
          6. 13.2.1.3.6 Page 1 / Register 8
          7. 13.2.1.3.7 Page 1 / Register 9
        2. 13.2.1.4 Page 44 Registers
          1. 13.2.1.4.1 Page 44 / Register 1
        3. 13.2.1.5 Page 253 Registers
          1. 13.2.1.5.1 Page 253 / Register 63
          2. 13.2.1.5.2 Page 253 / Register 64
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 13.2.1.2.19 Page 0 / Register 24
      2. 13.2.1.2.20 Page 0 / Register 27
      3. 13.2.1.2.21 Page 0 / Register 28
      4. 13.2.1.2.22 Page 0 / Register 29
      5. 13.2.1.2.23 Page 0 / Register 30
      6. 13.2.1.2.24 Page 0 / Register 32
      7. 13.2.1.2.25 Page 0 / Register 33
      8. 13.2.1.2.26 Page 0 / Register 34
      9. 13.2.1.2.27 Page 0 / Register 35
      10. 13.2.1.2.28 Page 0 / Register 36
      11. 13.2.1.2.29 Page 0 / Register 37
      12. 13.2.1.2.30 Page 0 / Register 40
      13. 13.2.1.2.31 Page 0 / Register 41
      14. 13.2.1.2.32 Page 0 / Register 42
      15. 13.2.1.2.33 Page 0 / Register 43
      16. 13.2.1.2.34 Page 0 / Register 44
      17. 13.2.1.2.35 Page 0 / Register 59
      18. 13.2.1.2.36 Page 0 / Register 60
      19. 13.2.1.2.37 Page 0 / Register 61
      20. 13.2.1.2.38 Page 0 / Register 62
      21. 13.2.1.2.39 Page 0 / Register 63
      22. 13.2.1.2.40 Page 0 / Register 64
      23. 13.2.1.2.41 Page 0 / Register 65
      24. 13.2.1.2.42 Page 0 / Register 80
      25. 13.2.1.2.43 Page 0 / Register 81
      26. 13.2.1.2.44 Page 0 / Register 82
      27. 13.2.1.2.45 Page 0 / Register 83
      28. 13.2.1.2.46 Page 0 / Register 84
      29. 13.2.1.2.47 Page 0 / Register 85
      30. 13.2.1.2.48 Page 0 / Register 86
      31. 13.2.1.2.49 Page 0 / Register 87
      32. 13.2.1.2.50 Page 0 / Register 90
      33. 13.2.1.2.51 Page 0 / Register 91
      34. 13.2.1.2.52 Page 0 / Register 92
      35. 13.2.1.2.53 Page 0 / Register 93
      36. 13.2.1.2.54 Page 0 / Register 94
      37. 13.2.1.2.55 Page 0 / Register 95
      38. 13.2.1.2.56 Page 0 / Register 108
      39. 13.2.1.2.57 Page 0 / Register 109
      40. 13.2.1.2.58 Page 0 / Register 114
      41. 13.2.1.2.59 Page 0 / Register 115
      42. 13.2.1.2.60 Page 0 / Register 118
      43. 13.2.1.2.61 Page 0 / Register 119
      44. 13.2.1.2.62 Page 0 / Register 120
      45. 13.2.1.2.63 Page 0 / Register 121
      46. 13.2.1.2.64 Page 0 / Register 122
      47. 13.2.1.2.65 Page 0 / Register 123
      48. 13.2.1.2.66 Page 0 / Register 124
      49. 13.2.1.2.67 Page 0 / Register 125
    2. 11.2 Layout Example
  12. 12Programming
    1. 12.1 Coefficient Data Formats
    2. 12.2 Power Down and Reset Behavior
  13. 13Register Maps
    1. 13.1 PCM5252 Register Map
      1. 13.1.1 Detailed Register Descriptions
        1. 13.1.1.1 Register Map Summary
        2. 13.1.1.2 Page 0 Registers
        3. 13.1.1.3 Page 1 Registers
        4. 13.1.1.4 Page 44 Registers
        5. 13.1.1.5 Page 253 Registers
      2. 13.1.2 PLL Tables for Software Controlled Devices
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  15. 15Mechanical, Packaging, and Orderable Information
  16. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  17. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

TI E2E Community : e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright© 2016, Texas Instruments Incorporated