SBASA30 December   2020 PCM6480-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Requirements: PDM Digital Microphone Interface
    13. 7.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 7.14 Timing Diagrams
    15. 7.15 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Analog Input Channel Configuration
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Microphone Bias
      6. 8.3.6  Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7  Digital PDM Microphone Record Channel
      8. 8.3.8  Signal-Chain Processing
        1. 8.3.8.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.8.2 Programmable Channel Gain Calibration
        3. 8.3.8.3 Programmable Channel Phase Calibration
        4. 8.3.8.4 Programmable Digital High-Pass Filter
        5. 8.3.8.5 Programmable Digital Biquad Filters
        6. 8.3.8.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.8.7 Configurable Digital Decimation Filters
          1. 8.3.8.7.1 Linear Phase Filters
            1. 8.3.8.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.8.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.8.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.8.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.8.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.8.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.8.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.8.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.8.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.8.7.2 Low-Latency Filters
            1. 8.3.8.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.8.7.3 Ultra-Low-Latency Filters
            1. 8.3.8.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.8.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      9. 8.3.9  Automatic Gain Controller (AGC)
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Four-Channel Analog Microphone and Four-Channel PDM Microphone Simultaneous Recording Using the PCM6480-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Interrupts, Status, and Digital I/O Pin Multiplexing

Certain events in the device may require host processor intervention and can be used to trigger interrupts to the host processor. Such event are an audio serial interface (ASI) bus error and input DC fault diagnostic faults. The device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:

  • Invalid FSYNC frequency
  • Invalid SBCLK to FSYNC ratio
  • Long pauses of the SBCLK or FSYNC clocks

When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for readback in the live fault status register bit INT_LIVE0, P1_R44 and is also latched to the fault status register bit INT_LTCH0, P0_R44, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears all latched fault statuses. The device can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.

When an input DC fault event is detected, the internal IRQ signal is asserted if the interrupt mask registers INT_MASK1, P0_R42 and INT_MASK2, P0_R43 are configured appropriately to unmask all desired fault diagnostics interrupts. Each input channel can be independently set for an interrupt mask. Table 8-44 and Table 8-45 list the mask settings available for the input DC diagnostics fault interrupts.

Table 8-44 Interrupt Mask Register 1 for DC Faults Diagnostic
P0_R42 : INT_MASK1 INTERRUPT MASK REGISTER 1 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
INT_MASK1[7] Channel 1 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[6] Channel 2 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[5] Channel 3 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[4] Channel 4 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[3] Channel 5 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[2] Channel 6 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[1] Short to VBAT_IN (when VBAT_IN is lower than MICBIAS) fault interrupt mask and unmask register bit
INT_MASK1[0] Reserved
Table 8-45 Interrupt Mask Register 2 for DC Faults Diagnostic
P0_R43 : INT_MASK2INTERRUPT MASK REGISTER 2 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
INT_MASK2[7]Open input fault interrupt mask and unmask register bit for all channels
INT_MASK2[6]Inputs shorted together fault interrupt mask and unmask register bit for all channels
INT_MASK2[5]INxP input shorted to ground fault interrupt mask and unmask register bit for all channels
INT_MASK2[4]INxM input shorted to ground fault interrupt mask and unmask register bit for all channels
INT_MASK2[3]INxP input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INT_MASK2[2]INxM input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INT_MASK2[1]INxP input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels
INT_MASK2[0]INxM input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels

The device supports the channel-specific input DC fault latched status registers for all channels from CH1_LTCH, P0_R46 to CH6_LTCH, P0_R51, which are read-only registers. The device also has a consolidated summary status register across channels for the input DC latched fault status register, CHx_LTCH, P0_R45 that the host can read to quickly know which channel fault has occurred. Reading the latched fault status registers, CH1_LTCH to CH6_LTCH, clears all the latched fault status including the summary status register, CHx_LTCH. Table 8-46 shows various input DC fault diagnostics status bits that are supported by the device.

Table 8-46 Input DC Faults Diagnostic Latched Status
P0_R46 : CH1_LTCHCHANNEL 1 INPUT FAULTS DIAGNOSTIC LATCHED STATUS
CH1_LTCH[7]Channel 1 open input fault detection status bit (self-clearing bit)
CH1_LTCH[6]Channel 1 inputs shorted together fault detection status bit (self-clearing bit)
CH1_LTCH[5]Channel 1 IN1P input shorted to ground fault detection status bit (self-clearing bit)
CH1_LTCH[4]Channel 1 IN1M input shorted to ground fault detection status bit (self-clearing bit)
CH1_LTCH[3]Channel 1 IN1P input shorted to MICBIAS fault detection status bit (self-clearing bit)
CH1_LTCH[2]Channel 1 IN1M input shorted to MICBIAS fault detection status bit (self-clearing bit)
CH1_LTCH[1]Channel 1 IN1P input shorted to VBAT_IN fault detection status bit (self-clearing bit)
CH1_LTCH[0]Channel 1 IN1M input shorted to VBAT_IN fault detection status bit (self-clearing bit)

Similarly, the DC faults diagnostic latched status for input channel 2 to channel 6 can be monitored using the CH2_LTCH (P0_R47) to CH6_LTCH (P0_R51) registers, respectively.

The device GPIOx pins can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that this pin can be wire-ANDed to the open-drain interrupt outputs of other devices.

The IRQ interrupt signal can either be configured as an active low or active high polarity by setting the INT_POL, P0_R40_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by programming the INT_EVENT[1:0], P0_R40_D[6:5] register bits. If the interrupts are configured as a series of pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine the cause of the interrupt.

The device also supports read-only live status registers that determine if all the channels are powered up or down and if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and P0_R119, DEV_STS1.

The device has a GPIO1 multifunction pin that can be configured for a desired specific function. Additionally, the PCM6480-Q1 has two more GPIO pins and two GPI pins supported that can be used in the system for the PDM microphone interface or for various other features. Table 8-47 shows all possible allocation of these multifunction pins for all the various features.

Table 8-47 Multifunction Pin Assignments
ROWPIN FUNCTIONGPIO1GPIO2GPIO3GPI1GPI2
GPIO1_CFG
[4:0]
GPIO2_CFG
[4:0]
GPIO3_CFG
[4:0]
GPI1_CFG[4:0]GPI2_CFG[4:0]
P0_R33[7:4]P0_R34[7:4]P0_R35[7:4]P0_R36[7:4]P0_R37[7:4]
APin disabledS(1)S (default)S (default)S (default)S (default)
BGeneral-purpose output (GPO)SSSNS(2)NS
CInterrupt output (IRQ)S (default)SSNSNS
DSecondary ASI output (SDOUT2)SSSNSNS
FMiCBIAS on/off input (BIASEN)SSSSS
GGeneral-purpose input (GPI)SSSSS
HMaster clock input (MCLK)SSSSS
IASI daisy-chain input (SDIN)SSSSS
S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.

Each GPIOx pin can be independently set for the desired drive configurations setting using the GPIOx_DRV[3:0] register bits. Table 8-48 lists the drive configuration settings.

Table 8-48 GPIOx Pins Drive Configuration Settings
P0_R33_D[3:0] : GPIO1_DRV[3:0]GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
000The GPIO1 pin is set to high impedance (floated)
001The GPIO1 pin is set to be driven active low or active high
010 (default)The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
011The GPIO1 pin is set to be driven active low or Hi-Z (floated)
100The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
101The GPIO1 pin is set to be driven Hi-Z (floated) or active high
110 and 111Reserved (do not use these settings)

Similarly, the GPIO2 and GPIO3 pins can be configured using the GPIO2_DRV(P0_R34) and GPIO3_DRV(P0_R35) register bits, respectively.

When configured as a general-purpose output (GPO), the GPIOx pin values can be driven by writing the GPIO_VAL P0_R38 registers. The GPIO_MON, P0_R39 register can be used to readback the status of the GPIOx and GPIx pins when configured as a general-purpose input (GPI).