SBASA30 December 2020 PCM6480-Q1
PRODUCTION DATA
In master mode operation with I2S or LJ format, the device generates FSYNC half a cycle earlier than the normal protocol timing behavior expected. This timing behavior can still function for most of the system, however for further details and a suggested workaround for this weakness, see the Configuring and Operating TLV320ADCx140 as Audio Bus Master application report.
The automatic gain controller (AGC) feature has some limitation when using sampling rates lower than 44.1 kHz. For further details about this limitation, see the Using the Automatic Gain Controller in PCM6xx0-Q1 application report.
For I2C operation, if the ADDR0_SCLK pin is tied high, then the I2C bus must remain idle (which means the SDA_SSZ and SCL_MOSI pins must be high) when the SHDNZ pin is released from low to high.