SBASA30 December   2020 PCM6480-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Requirements: PDM Digital Microphone Interface
    13. 7.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 7.14 Timing Diagrams
    15. 7.15 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Analog Input Channel Configuration
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Microphone Bias
      6. 8.3.6  Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7  Digital PDM Microphone Record Channel
      8. 8.3.8  Signal-Chain Processing
        1. 8.3.8.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.8.2 Programmable Channel Gain Calibration
        3. 8.3.8.3 Programmable Channel Phase Calibration
        4. 8.3.8.4 Programmable Digital High-Pass Filter
        5. 8.3.8.5 Programmable Digital Biquad Filters
        6. 8.3.8.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.8.7 Configurable Digital Decimation Filters
          1. 8.3.8.7.1 Linear Phase Filters
            1. 8.3.8.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.8.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.8.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.8.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.8.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.8.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.8.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.8.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.8.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.8.7.2 Low-Latency Filters
            1. 8.3.8.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.8.7.3 Ultra-Low-Latency Filters
            1. 8.3.8.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.8.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      9. 8.3.9  Automatic Gain Controller (AGC)
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Four-Channel Analog Microphone and Four-Channel PDM Microphone Simultaneous Recording Using the PCM6480-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

The PCM6480-Q1 is a scalable device that consists of high-performance, low-power, flexible, multichannel, audio analog-to-digital converters (ADCs) with extensive feature integration. This device is intended for automotive applications such as vehicle cabin active noise cancellation, hands-free in-vehicle communication, emergency call, and multimedia applications. The PCM6480-Q1 is a high performance audio converter that supports simultaneous sampling of up to a 4-channel analog microphone or a line input along with up to a 4-channel digital pulse density-modulation (PDM) microphone input. The high dynamic range of this device enables far-field audio recording with high fidelity. This device integrates a host of features that reduce cost, board space, and power consumption in space-constrained automotive sub-system designs. Package, performance, and device-compatible configuration registers make this device well suited for scalable system designs.

The PCM6480-Q1 consists of the following blocks:

  • 4-channel, multibit, high-performance delta-sigma (ΔΣ) ADCs
  • 4-channel pulse density modulation (PDM) digital microphone interface with high-performance decimation filter
  • Configurable single-ended or differential audio inputs with high voltage signal swing
  • High-voltage, low-noise programmable microphone bias output
  • Highly flexible, comprehensive input fault diagnostic
  • Automatic gain controller (AGC)
  • Programmable decimation filters with linear-phase or low-latency filter
  • Programmable channel gain, volume control, and biquad filters for each channel
  • Programmable phase and gain calibration with fine resolution for each channel
  • Programmable high-pass filter (HPF) and digital channel mixer
  • Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply operation

Communication to the PCM6480-Q1 for configuring the control registers is supported using an I2C or SPI interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices.

The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover, the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the shared TDM bus timing requirements and board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

Table 8-1 lists the reference abbreviations used throughout this document to registers that control the device.

Table 8-1 Abbreviations for Register References
REFERENCE ABBREVIATION DESCRIPTION EXAMPLE
Page y, register z, bit k Py_Rz_Dk Single data bit. The value of a single bit in a register. Page 4, register 36, bit 0 = P4_R36_D0
Page y, register z, bits k-m Py_Rz_D[k:m] Range of data bits. A range of data bits (inclusive). Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page y, register z Py_Rz One entire register. All eight bits in the register as a unit. Page 4, register 36 = P4_R36
Page y, registers z-n Py_Rz-Rn Range of registers. A range of registers in the same page. Page 4, registers 36, 37, 38 = P4_R36-R38