SBASA30 December   2020 PCM6480-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Requirements: PDM Digital Microphone Interface
    13. 7.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 7.14 Timing Diagrams
    15. 7.15 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Analog Input Channel Configuration
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Microphone Bias
      6. 8.3.6  Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7  Digital PDM Microphone Record Channel
      8. 8.3.8  Signal-Chain Processing
        1. 8.3.8.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.8.2 Programmable Channel Gain Calibration
        3. 8.3.8.3 Programmable Channel Phase Calibration
        4. 8.3.8.4 Programmable Digital High-Pass Filter
        5. 8.3.8.5 Programmable Digital Biquad Filters
        6. 8.3.8.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.8.7 Configurable Digital Decimation Filters
          1. 8.3.8.7.1 Linear Phase Filters
            1. 8.3.8.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.8.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.8.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.8.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.8.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.8.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.8.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.8.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.8.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.8.7.2 Low-Latency Filters
            1. 8.3.8.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.8.7.3 Ultra-Low-Latency Filters
            1. 8.3.8.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.8.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.8.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.8.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.8.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.8.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.8.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      9. 8.3.9  Automatic Gain Controller (AGC)
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Four-Channel Analog Microphone and Four-Channel PDM Microphone Simultaneous Recording Using the PCM6480-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC PERFORMANCE FOR LINE INPUT RECORDING
Differential input full-scale AC signal voltage AC-coupled input, input fault diagnostic not supported 10 VRMS
DC-coupled input, DC common-mode voltage INxP = INxM = 7.1 V, input fault diagnostic not supported
Single-ended input full-scale AC signal voltage AC-coupled input, input fault diagnostic not supported 5 VRMS
DC-coupled input, DC common-mode voltage INxP = INxM = 7.1 V, input fault diagnostic not supported
SNR Signal-to-noise ratio, A-weighted(1) (2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 105 110 dB
IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 110
IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 101
DR Dynamic range, A-weighted(2) IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 110 dB
IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 110
IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 101
THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –95 –78 dB
IN1 differential DC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –95
IN1 differential DC-coupled input selected and –13-dB full-scale AC signal input, 12-dB channel gain –91
Channel gain control range Programmable 1-dB steps 0 42 dB
ADC PERFORMANCE FOR MICROPHONE INPUT RECORDING
Differential input full-scale AC signal voltage(3) AC-coupled input, input fault diagnostic not supported. CHx_MIC_RANGE register bit is set to high. 10 VRMS
DC-coupled input, DC differential common-mode voltage INxP –  INxM > 3.4 V, DC common-mode voltage INxP < (MICBIAS – 1.7 V) and DC common-mode voltage INxM > 1.7 V. CHx_MIC_RANGE register bit is set to high to support AC differential signal max swing > 2 Vrms(4).
SNR Signal-to-noise ratio, A-weighted(1) (2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 110 dB
IN1 differential DC-coupled input selected and AC-signal shorted to ground, DC differential common-mode voltage IN1P –  IN1M < 5.0 V, 0-dB channel gain 105 110
DR Dynamic range, A-weighted(2) IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 110 dB
IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, DC differential common-mode voltage IN1P –  IN1M < 5.0 V, 0-dB channel gain 110
THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –92 dB
IN1 differential DC-coupled input selected and –15-dB full-scale AC signal input, 0-dB channel gain –90 –78
Channel gain control range Programmable 1-dB steps 0 42 dB
ADC OTHER PARAMETERS
Input impedance Differential input, between INxP and INxM 50 kΩ
Single-ended input, between INxP and INxM 25
Digital volume control range Programmable 0.5-dB steps –100 27 dB
Output data sample rate Programmable 7.35 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 12 Hz
Interchannel isolation –1-dB full-scale AC signal line-in input to non measurement channel –134 dB
Interchannel gain mismatch –6-dB full-scale AC signal line-in input, 0-dB channel gain 0.1 dB
Interchannel phase mismatch 1-kHz sinusoidal signal 0.01 Degrees
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 92 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 0-dB channel gain, 1-VRMS AC input, 1-kHz signal on both pins and measure level at output, CHx_CFG0 D3-2 register bits set to 2b'10 to configure device in high CMRR performance mode 70 dB
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS 6.8 µVRMS
MICBIAS voltage Programmable 0.5-V steps 5 9 V
MICBIAS current drive MICBIAS voltage 9 V 80 mA
MICBIAS load regulation MICBIAS voltage 9 V, measured up to maximum load 0 1 %
MICBIAS over current protection threshold MICBIAS voltage 9 V 82 mA
INPUT DIAGNOSTICS
Fault monitoring repetition rate Programmable, DC-coupled input 1 4 8 ms
Fault response time Fault monitoring repetition rate 4-ms, DC-coupled input 16 ms
Threshold voltage for (INxx – AVSS) input shorted to ground Programmable 60-mV steps, DC-coupled input 0 900 mV
Threshold voltage for (INxP – INxM) input shorted together Programmable 30-mV steps, DC-coupled input 0 450 mV
Threshold voltage for (MICBIAS – INxx) input shorted to MICBIAS Programmable 30-mV steps, DC-coupled input 0 450 mV
Threshold voltage for (VBAT – INxx) input shorted to VBAT_IN Programmable 30-mV steps, DC-coupled input 0 450 mV
DIGITAL I/O
VIL(SHDNZ) Low-level digital input logic voltage threshold SHDNZ pin –0.3 0.25 × IOVDD V
VIH(SHDNZ) High-level digital input logic voltage threshold SHDNZ pin 0.75 × IOVDD IOVDD + 0.3 V
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V
All digital pins except SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in hardware shutdown mode SHDNZ = 0, all device external clocks stopped 0.5 µA
IBSTVDD 0.1
IIOVDD 0.1
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped 4 µA
IBSTVDD 0.1
IIOVDD 0.1
IAVDD Current consumption when MICBIAS ON, MICBIAS voltage 9 V, 40 mA load, ADC off fS = 48 kHz, BCLK = 256 × fS 2.1 mA
IBSTVDD 162.5
IIOVDD 0.01
IAVDD Current consumption with ADC 2-channel analog input operation at fS 16-kHz MICBIAS off, PLL on, BCLK = 512 × fS 13.5 mA
IBSTVDD 0
IIOVDD 0.1
IAVDD Current consumption with ADC 2-channel analog input operation at fS 48-kHz MICBIAS off, PLL off, BCLK = 512 × fS 13.5 mA
IBSTVDD 0
IIOVDD 0.1
IAVDD Current consumption with ADC 4-channel analog input operation at fS 48-kHz MICBIAS off, PLL on, BCLK = 256 × fS 24.7 mA
IBSTVDD 0
IIOVDD 0.2
IAVDD Current consumption with 4-channel digial PDM input operation at fS 48 kHz MICBIAS off, PLL on, BCLK = 256 × fS, GPIO2 and GPIO3 configured as PDMCLK = 64 × fS 9.7 mA
IBSTVDD 0
IIOVDD 3.1
IAVDD Current consumption with ADC 4-channel analog input and 4-channel digial PDM input operation at fS 48 kHz MICBIAS off, PLL on, BCLK = 256 × fS, GPIO2 and GPIO3 configured as PDMCLK = 64 × fS 28.5 mA
IBSTVDD 0
IIOVDD 3.2
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) Microphone inputs support a 2 VRMS differential input full-scale AC signal voltage, if the CHx_MIC_RANGE register bit is set to low (default value). However, if the input DC common-mode differential voltage is higher than 4 V, then TI recommends setting the CHx_MIC_RANGE register bit high to avoid any saturation resulting from the high input DC common-mode differential voltage.
(4) If the CHx_MIC_RANGE register bit is set to high (default value is low) in DC-coupled input configuration mode, then the input differential DC common-mode along with input differential AC signal must be less than 10 VRMS for differential input configuration mode. Similarly, for single-ended input configuration mode, the input DC common-mode voltage along with the input AC signal must be less than 5 VRMS .