SBAS495D June 2010 – August 2021 PCM9211
PRODUCTION DATA
Figure 7-27 shows the functional timing diagram for a single write operation on the serial control port. MS is held at 1 until a register must be written. To start the register write cycle, MS should be set to 0. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle has been completed, MS is set to 1 to latch the data into the indexed mode control register.
Channel status data are available from the Channel Status registers. To read the first 48 bits of the Channel Status registers accurately, the read should be started 48fS after the start of the block. However, once MS is pulled to 0, there are no time requirements in which to read the data because the registers are locked.
Both INT0 and INT1 can also be masked to highlight when the Channel Status has been updated. In many cases, Channel Status does not change during playback (of a movie or music). Once the source changes, though, the Channel Status changes. This change causes an interrupt, which can then be used to trigger the DSP to read the Channel Status registers. The interrupt source is called OCSRNWx (Output Channel Status Renewal).
The OCSRNWx flag can be held in the INTx register, or masked and brought out to the ERR/INT0 or NPCM/INT1 pin.