SLASEC8C February   2017  – February 2023 PGA460-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Supply Regulators Characteristics
    6. 6.6  Transducer Driver Characteristics
    7. 6.7  Transducer Receiver Characteristics
    8. 6.8  Analog to Digital Converter Characteristics
    9. 6.9  Digital Signal Processing Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 High-Voltage I/O Characteristics
    12. 6.12 Digital I/O Characteristics
    13. 6.13 EEPROM Characteristics
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Supply Block
      2. 7.3.2  Burst Generation
        1. 7.3.2.1 Using Center-Tap Transformer
        2. 7.3.2.2 Direct Drive
        3. 7.3.2.3 Other Configurations
      3. 7.3.3  Analog Front-End
      4. 7.3.4  Digital Signal Processing
        1. 7.3.4.1 Ultrasonic Echo—Band-Pass Filter
        2. 7.3.4.2 Ultrasonic Echo–Rectifier, Peak Hold, Low-Pass Filter, and Data Selection
        3. 7.3.4.3 Ultrasonic Echo—Nonlinear Scaling
        4. 7.3.4.4 Ultrasonic Echo—Threshold Data Assignment
        5. 7.3.4.5 Digital Gain
      5. 7.3.5  System Diagnostics
        1. 7.3.5.1 Device Internal Diagnostics
      6. 7.3.6  Interface Description
        1. 7.3.6.1 Time-Command Interface
          1. 7.3.6.1.1 RUN Commands
          2. 7.3.6.1.2 CONFIGURATION/STATUS Command
        2. 7.3.6.2 USART Interface
          1. 7.3.6.2.1 USART Asynchronous Mode
            1. 7.3.6.2.1.1 Sync Field
            2. 7.3.6.2.1.2 Command Field
            3. 7.3.6.2.1.3 Data Fields
            4. 7.3.6.2.1.4 Checksum Field
            5. 7.3.6.2.1.5 PGA460-Q1 UART Commands
            6. 7.3.6.2.1.6 UART Operations
              1. 7.3.6.2.1.6.1 No-Response Operation
              2. 7.3.6.2.1.6.2 Response Operation (All Except Register Read)
              3. 7.3.6.2.1.6.3 Response Operation (Register Read)
            7. 7.3.6.2.1.7 Diagnostic Field
            8. 7.3.6.2.1.8 USART Synchronous Mode
          2. 7.3.6.2.2 One-Wire UART Interface
          3. 7.3.6.2.3 Ultrasonic Object Detection Through UART Operations
        3. 7.3.6.3 In-System IO-Pin Interface Selection
      7. 7.3.7  Echo Data Dump
        1. 7.3.7.1 On-Board Memory Data Store
        2. 7.3.7.2 Direct Data Burst Through USART Synchronous Mode
      8. 7.3.8  Low-Power Mode
        1. 7.3.8.1 Time-Command Interface
        2. 7.3.8.2 UART Interface
      9. 7.3.9  Transducer Time and Temperature Decoupling
        1. 7.3.9.1 Time Decoupling
        2. 7.3.9.2 Temperature Decoupling
      10. 7.3.10 Memory CRC Calculation
      11. 7.3.11 Temperature Sensor and Temperature Data-Path
      12. 7.3.12 TEST Pin Functionality
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 UART and USART Communication Examples
    6. 7.6 Register Maps
      1. 7.6.1 EEPROM Programming
      2. 7.6.2 Register Map Partitioning and Default Values
      3. 7.6.3 REGMAP Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transducer Types
    2. 8.2 Typical Applications
      1. 8.2.1 Transformer-Driven Method
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct-Driven (Transformer-Less) Method
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.16 Typical Characteristics

10 pulses, 400-mA current limit, 58.6-kHz driving frequency

GUID-1AE7F6A3-C713-46AA-B8B4-B3A4CABE16A5-low.gif
TDK EPCOS B78416A2232A003 transformer
muRata MA58MF14-7N transducer
OUTA/B Gate Driver is scaled up by 10 times
Figure 6-1 Driver Stage and Resulting Transducer Behavior
GUID-3FE0C22D-A8D6-47BE-BB35-88BDE057908B-low.gif
TDK EPCOS B78416A2232A003 transformer
muRata MA58MF14-7N transducer
LNA analog output is scaled and shifted. Actual signal is 100 times smaller and common mode is shifted up by 0.9 V
Figure 6-2 Receiver AFE Output Post-LNA Object at 35 cm