SLASEJ4C April   2017  – February 2023 PGA460

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Supply Regulators Characteristics
    6. 6.6  Transducer Driver Characteristics
    7. 6.7  Transducer Receiver Characteristics
    8. 6.8  Analog to Digital Converter Characteristics
    9. 6.9  Digital Signal Processing Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 High-Voltage I/O Characteristics
    12. 6.12 Digital I/O Characteristics
    13. 6.13 EEPROM Characteristics
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Supply Block
      2. 7.3.2  Burst Generation
        1. 7.3.2.1 Using Center-Tap Transformer
        2. 7.3.2.2 Direct Drive
        3. 7.3.2.3 Other Configurations
      3. 7.3.3  Analog Front-End
      4. 7.3.4  Digital Signal Processing
        1. 7.3.4.1 Ultrasonic Echo—Band-Pass Filter
        2. 7.3.4.2 Ultrasonic Echo–Rectifier, Peak Hold, Low-Pass Filter, and Data Selection
        3. 7.3.4.3 Ultrasonic Echo—Nonlinear Scaling
        4. 7.3.4.4 Ultrasonic Echo—Threshold Data Assignment
        5. 7.3.4.5 Digital Gain
      5. 7.3.5  System Diagnostics
        1. 7.3.5.1 Device Internal Diagnostics
      6. 7.3.6  Interface Description
        1. 7.3.6.1 Time-Command Interface
          1. 7.3.6.1.1 RUN Commands
          2. 7.3.6.1.2 CONFIGURATION/STATUS Command
        2. 7.3.6.2 USART Interface
          1. 7.3.6.2.1 USART Asynchronous Mode
            1. 7.3.6.2.1.1 Sync Field
            2. 7.3.6.2.1.2 Command Field
            3. 7.3.6.2.1.3 Data Fields
            4. 7.3.6.2.1.4 Checksum Field
            5. 7.3.6.2.1.5 PGA460 UART Commands
            6. 7.3.6.2.1.6 UART Operations
              1. 7.3.6.2.1.6.1 No-Response Operation
              2. 7.3.6.2.1.6.2 Response Operation (All Except Register Read)
              3. 7.3.6.2.1.6.3 Response Operation (Register Read)
            7. 7.3.6.2.1.7 Diagnostic Field
            8. 7.3.6.2.1.8 USART Synchronous Mode
          2. 7.3.6.2.2 One-Wire UART Interface
          3. 7.3.6.2.3 Ultrasonic Object Detection Through UART Operations
        3. 7.3.6.3 In-System IO-Pin Interface Selection
      7. 7.3.7  Echo Data Dump
        1. 7.3.7.1 On-Board Memory Data Store
        2. 7.3.7.2 Direct Data Burst Through USART Synchronous Mode
      8. 7.3.8  Low-Power Mode
        1. 7.3.8.1 Time-Command Interface
        2. 7.3.8.2 UART Interface
      9. 7.3.9  Transducer Time and Temperature Decoupling
        1. 7.3.9.1 Time Decoupling
        2. 7.3.9.2 Temperature Decoupling
      10. 7.3.10 Memory CRC Calculation
      11. 7.3.11 Temperature Sensor and Temperature Data-Path
      12. 7.3.12 TEST Pin Functionality
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 UART and USART Communication Examples
    6. 7.6 Register Maps
      1. 7.6.1 EEPROM Programming
      2. 7.6.2 Register Map Partitioning and Default Values
      3. 7.6.3 REGMAP Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transducer Types
    2. 8.2 Typical Applications
      1. 8.2.1 Transformer-Driven Method
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct-Driven (Transformer-Less) Method
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.6.1.2 CONFIGURATION/STATUS Command

The CONFIGURATION/STATUS command is used for the following:

  • PGA460 internal parameter configuration
  • Time-varying gain and threshold setup
  • EEPROM programing
  • Diagnostics and temperature measurements
  • Echo data-dump function

When the CONFIGURATION/STATUS command is issued, the remaining data is transferred by using bit-like communication where a logical 1 and logical 0 are encoded (see GUID-B708BCB0-1646-4112-AEF4-686990C62507.html#X5782). #X6723 and #X6098 show a full-length CONFIGURATION/STATUS command.

Figure 7-15 Time-Command Interface CONFIGURATION/STATUS Command—Write
Figure 7-16 Time-Command Interface CONFIGURATION/STATUS Command—Read

As indicated, each CONFIGURATION/STATUS command frame consists of three data segments: subcommand field, data field, and frame checksum. The subcommands are defined and ordered by a 4-bit index field, where each subcommand can have a different data length in the data segment of the frame. Table 7-2 lists all PGA460 subcommands ordered according to their respective index.

Table 7-2 Time-Command Interface Subcommand Description#X1019
INDEXDESCRIPTIONDATA LENGTH (BITS)ACCESSEE
0Temperature value8RN
1Transducer frequency diagnostic value824RN
Decay period time diagnostic value8
Noise level diagnostic value8
2Driver frequency (FREQ)8R/WY
3Number of burst pulses for Preset1 (P1_PULSE)518R/WY
Number of burst pulses for Preset2 (P2_PULSE)5
Threshold comparator Deglitch (THR_CMP_DEG)4
Burst pulses dead-time (PULSE_DT)4
4Record time length for Preset1 (P1_REC)48R/WY
Record time length for Preset2 (P2_REC)4
5Threshold assignment for Preset1 (P1_THR_0 to P1_THR_15)#X2692124R/WN
6Threshold assignment for Preset2 (P2_THR_0 to P2_THR_15)#X2692124R/WN
7Band-pass filter bandwidth (BPF_BW)242R/WY
Initial AFE gain (GAIN_INIT)6
Low-pass filter cutoff frequency (LPF_CO)2
Nonlinear scaling noise level (NOISE_LVL)5
Nonlinear scaling exponent (SCALE_K)1
Nonlinear scaling time offset (SCALE_N)2
Temperature-scale gain (TEMP_GAIN)4
Temperature-scale offset (TEMP_OFF)4
P1 digital gain start threshold (P1_DIG_GAIN_LR_ST)2
P1 digital long-range gain (P1_DIG_GAIN_LR)3
P1 digital short-range gain (P1_DIG_GAIN_SR)3
P2 digital gain start threshold (P2_DIG_GAIN_LR_ST)2
P2 digital long-range gain (P2_DIG_GAIN_LR)3
P2 digital short-range gain (P2_DIG_GAIN_SR)3
8Time-varying gain Assignment (TV_GAIN0 to TV_GAIN6)56R/WY
9User-data memory (USER_1 to USER_20)160R/WY
10Frequency diagnostic window length (FDIAG_LEN)446R/WY
Frequency diagnostic start time (FDIAG_START)4
Frequency diagnostic error time threshold (FDIAG_ERR_TH)3
Saturation diagnostic level (SAT_TH)4
P1 nonlinear scaling (P1_NLS_EN)1
P2 nonlinear scaling (P2_NLS_EN)1
Supply overvoltage shutdown threshold (VPWR_OV_TH)2
Sleep mode timer (LPM_TMR)2
Voltage diagnostic threshold (FVOLT_ERR_TH)3
AFE gain range (AFE_GAIN_RNG)2
Low-power mode enable (LPM_EN)1
Decouple time and temperature select (DECPL_TEMP_SEL)1
Decouple time and temperature value (DECPL_T)4
Disable current limit (DIS_CL)1
Reserved1
Driver current limit for Preset1 (CURR_LIM1)6
Driver current limit for Preset2 (CURR_LIM2)6
11Echo data-dump enable (DATADUMP_EN)18R/WN
EEPROM programming password (0xD)4
EEPROM programming successful (EE_PRGM_OK)1
Reload EEPROM (EE_RLOAD)1
Program EEPROM (EE_PRGM)1
12Echo data-dump values#X10741024RN
13EEPROM user-bulk command (0x00 to 0x2B)#X9939352R/WY
14Reserved
15EEPROM CRC value (EE_CRC)
THR_CRC value (THR_CC)		16RY
(1) Including the threshold level offset parameter (TH_Px_OFF).
(2) Echo dump memory is an array of 128 samples, 8 bits/sample.
(3) For index 13, byte 0x2B is read-only, when an index-13 write command is sent, the byte-2B data field will have no effect on the EE_CRC value.
(4) The acronyms used in this table (for example, CURR_LIM1) are the same as those used in the GUID-ED773D30-2D5D-4A9D-B0E9-278B351A9705.html#TITLE-SLASEC8X3442 section.

The frame checksum value is generated by both the controller and peripheral devices, and is added after the data field, while calculated as the inverted eight bit sum with carry-over on all bits in the frame. The checksum calculation occurs byte-wise starting from the most-significant bit (MSB) which is the read-write (R/W) bit in the PGA460 write operation while for PGA460 read operation, this is the MSB of the data field. In cases where the number of bits on which the checksum field is calculated is not a multiple of eight, then the checksum operation pads trailing zeros until the closest multiple eight is achieved. Zero padding is only required for the checksum calculation. The zero-padded bits should not actually be transmitted over the IO-TCI interface.

The following example, is one example of a frame checksum calculation showing the PGA460 write operation of for subcommand Index 7 (42 data bits):

  • Total number of bits for checksum generation: 1 R/W bit, 4 bits index value, 42 bits data values. The total number of bits is 47.
  • Because the checksum is calculated byte-wise, 1 trailing zero is added to achieve 6 full bytes.
  • #X9668 shows additional checksum calculation.

The following example, is a second example of a frame checksum calculation showing the PGA460 read operation of for subcommand index 8:

  • Total number of bits for checksum generation by the PGA460 device: 56 bits data values + 8 command bits. The total number of bits is 64.
  • The 8 command bits are equal to 4-zero bits + Index[3:0] = 8 command bits which is the first byte used in the checksum calculation.
  • No trailing zeros added because the number of bits is already 56 or 7 bytes.
  • #X9668 shows additional checksum calculation.

GUID-5C813DFD-B8DD-48FD-B190-8AD7FB1E826E-low.gifFigure 7-17 Checksum Calculation

In addition, when a PGA460 write operation is issued, the PGA460 device implements an acknowledgment bit response to signify a correct data transfer occurred. In this case, if the CONFIGURATION/STATUS command time period is not detected properly, the PGA460 device does issue an acknowledgment bit. If the CONFIGURATION/STATUS command-time period is detected properly but the checksum of the transferred frame is not correct, then the PGA460 device transmits a logical 0 acknowledgment. If the CONFIGURATION/STATUS command-time period is detected properly and the checksum value matches the correct checksum, then the PGA460 device transmits a logical 1 acknowledgment.

In the case of a bit-like communication (PGA460 actively serving CONFIGURATION/STATUS command) when the bit stream is interrupted with another time command (either RUN or CONFIGURATION), the PGA460 device decodes this event as a bit-timed event in which case the execution of the initial CONFIGURATION/STATUS command continues until either a time-out error event is reached or, in the case of a continuous data transfer, the PGA460 frame checksum invalidates the incorrectly transferred frame. In the case where the bit-stream is valid but is longer than expected, the PGA460 executes on the correctly transferred frame but ignores the rest of the bit-stream.

If, during PGA460 IDLE state, the time-command interface receives a time command with pulse duration outside the limits of any of the commands, this condition is ignored and the PGA460 device remains in the IDLE state until a valid time command is received. In this case, the PGA460 does not respond with a negative acknowledgment.