SBOSAE0B April   2023  – September 2023 PGA855

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain Control
      2. 8.3.2 Input Protection
      3. 8.3.3 Output Common-Mode Pin
      4. 8.3.4 Using the Fully Differential Output Amplifier to Shape Noise
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Linear Operating Input Range
    2. 9.2 Typical Applications
      1. 9.2.1 ADS127L11 and ADS127L21, 24-Bit, Delta-Sigma ADC Driver Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 ADS8900B 20-Bit SAR ADC Driver Circuit
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Detailed Design Procedure

The ADS8900B requires an input common-mode voltage within the range of VREF / 2 ±100 mV. The PGA855 VOCM pin is set to a nominal voltage of approximately 2.58 V. The VOCM voltage is purposely set to a voltage slightly greater than VREF / 2 to maximize the output voltage swing range of the PGA855, while allowing margin for the VOCM offset voltage error and drift variation. The VOCM voltage is generated by feeding the REF5050 reference through an 18.7 kΩ- to 0 kΩ voltage divider implemented with 0.1% tolerance resistors. An additional RC filter with R = 1 kΩ, C = 10 nF is used in close proximity to the VOCM pin as shown on Figure 9-9.

The R-C-R differential low-pass filter at the input of the PGA helps reduce EMI/RFI high frequency extrinsic noise. This filter can be customized per the bandwidth and application requirements.

Two first-order filters are implemented with the PGA855 circuit. The first filter is provided by CFB in parallel with the PGA 5‑kΩ feedback resistors. The PGA resistors are ±15% absolute tolerance, such as, consider the effect of the tolerance on the filter cutoff frequency, the filter frequency changes to 126 kHz. At this tolerance, the filter maintains –0.1 dB flatness to 24 kHz.

There is flexibility of modifying the CFB capacitor value to adjust bandwidth, with the trade-off on the broadband noise of the circuit.

The second filter placed directly at the ADS8900B inputs works as a charge reservoir to filter the sampled input of the ADC. The charge reservoir reduces the instantaneous charge demand of the amplifier, maintaining low distortion that otherwise can degrade because of incomplete amplifier settling. The RC filter combination (RFIL, CDIFF) is optimized for the SAR ADC sample and hold settling. This combination reduces nonlinear charge kickback of the SAR ADC and is optimized for best THD performance. This combination allows for the best trade-off between harmonic distortion while maintaining stability of the PGA output stage.

High-grade C0G (NPO) are used everywhere in the signal path (CIN_DIFF, CIN_CM, CFB, CDIFF, CCM) for the low distortion properties.

The results are shown in Table 9-5, which includes the typical signal-to-noise ratio (SNR) and total harmonic distortion (THD) of the PGA855 driving the ADS8900B SAR ADC. For the SNR and THD measurements, a 1-kHz differential signal is applied. The signal amplitude is adjusted to produce a PGA855 output at –0.5 dBFS of the ADC full-scale range. Table 9-5 shows the equivalent input voltage amplitude signal for different PGA855 gain configurations. At gain = 1 V/V, the design achieves a –121.4‑dB THD and 101.2‑dB SNR.

Table 9-5 PGA855 and ADS8900B FFT Data Summary: fSAMPLE = 1 MSPS, fIN = 1 kHz
PGA GAIN (V/V) INPUT AMPLITUDE (VPP) ADC SIGNAL POWER (dBFS) SNR (dB) THD (dB) ENOB (Bits)
0.125 40.10 –6.0 95.9 –118.2 15.6
0.25 36.48 –0.8 101.0 –118.6 16.5
0.5 18.24 –0.8 101.2 –121.0 16.5
1 9.12 –0.8 101.2 –121.7 16.5
2 4.56 –0.8 100.5 –121.6 16.4
4 2.28 –0.8 99.5 –121.3 16.2
8 1.14 –0.8 97.4 –119.4 15.9
16 0.58 –0.8 93.6 –117.3 15.2