Attention to good layout practices is always recommended. For best operational performance of the device, use good PCB layout practices, including:
- To avoid converting common-mode signals into
differential signals and thermal electromotive forces (EMFs), make sure that
both input paths are symmetrical and well-matched for source impedance and
capacitance.
- Noise can propagate into analog circuitry through
the power pins of the device and of the circuit as a whole. Bypass capacitors reduce the
coupled noise by providing low-impedance power sources local to the analog circuitry.
- Connect low-ESR, 0.1-µF ceramic bypass capacitors
between each supply pin and ground, placed as close as possible to the device. A
single bypass capacitor from VS+ and VLVDD to ground is
applicable for single-supply applications.
- To reduce parasitic coupling, run the input
traces as far away as possible from the supply or output traces. If these traces cannot
be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
- Leakage on the FDA_IN+ and FDA_IN– pins can cause in a dc offset
error in the output voltages. Additionally, excessive parasitic capacitance at these
pins can result in decreased phase margin and affect the stability of the output stage.
If these pins are not used to implement deliberate capacitive feedback, follow best
practices to minimize leakage and parasitic capacitance.
- Follow best practices to minimize
leakage and parasitic capacitance, which includes implementing keep-out areas in
any ground planes that lie immediately below the input pins.
- Minimize the number of thermal junctions. If possible, route the signal path
using a single layer without vias.
- Keep sufficient distance from major thermal
energy sources (circuits with high power dissipation). If not possible, place the device
so that the effects of the thermal energy source on the high and low sides of the
differential signal path are evenly matched.
- Keep the traces as short as possible.