SBOSAE0B April   2023  – September 2023 PGA855

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain Control
      2. 8.3.2 Input Protection
      3. 8.3.3 Output Common-Mode Pin
      4. 8.3.4 Using the Fully Differential Output Amplifier to Shape Noise
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Linear Operating Input Range
    2. 9.2 Typical Applications
      1. 9.2.1 ADS127L11 and ADS127L21, 24-Bit, Delta-Sigma ADC Driver Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 ADS8900B 20-Bit SAR ADC Driver Circuit
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at TA = 25 °C, VS = VSOUT = ±15 V, VICM = VOCM is at mid-supply, RL = 10 kΩ, and G = 1 V/V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Differential offset voltage (input referred) G = 1 to 16 ±70 ±350 µV
G < 1 ±70/G ±350/G
Differential offset voltage drift (input referred) G = 1 to 16, TA = –40°C to +125°C ±0.3 ±1.0 µV/°C
G < 1, TA = –40°C to +125°C ±0.3/G ±1.0/G
PSRR Power-supply rejection ratio ±4 V ≤ VS ≤ ±18 V, RTI G = 0.125 102 108 dB
G = 0.25 108 114 dB
G = 0.5 114 120
G = 1 120 126
G = 2 120 126
G = 4 120 132
G = 8 120 136
G = 16 120 140
zid Differential impedance 100 || 1 GΩ || pF
zic Common-mode impedance 100 || 7 GΩ || pF
VI Input voltage VS = ±4 V to ±18 V, TA = –40°C to +125°C (VS–) + 2.5 (VS+) – 2.5 V
CMRR Common-mode rejection ratio At dc to 60 Hz,
VICM = ± 10 V,
TA = –40°C to +125°C,
RTI		 G = 0.125 64 82 dB
G = 0.25 70 88
G = 0.5 76 94
G = 1 82 100
G = 2 88 106
G = 4 94 112
G = 8 100 118
G = 16 106 124
BIAS CURRENT
IB Input bias current 0.5 1.8 nA
TA = –40°C to +125°C 1
Input bias current drift TA = –40°C to +125°C 10 pA/°C
IOS Input offset current 0.5 1 nA
TA = –40°C to +125°C 1
Input offset current drift TA = –40°C to +125°C 10 pA/°C
NOISE VOLTAGE
eNI Input-referred voltage noise density f = 1 kHz G = 16 7.8 nV/√Hz
G = 8 8.0
G = 4 8.6
G = 2 12.6
G = 1 21.6
G = 0.5 42
G = 0.25 84
G = 0.125 168
ENI Input-referred voltage noise fB = 0.1 Hz to 10 Hz G = 16 0.26 µVPP
G = 8 0.27
G = 4 0.29
G = 2 0.44
G = 1 0.8
G = 0.5 1.6
G = 0.25 3.2
G = 0.125 6.4
iN Input current noise density f = 1 kHz 0.3 pA/√Hz
IN Input current noise fB = 0.1 Hz to 10 Hz 13 pAPP
GAIN
Differential gain range 0.125 16 V/V
GE Differential gain error G = 0.25, 0.5, 2, 4 ±0.02 ±0.05 %
G = 1 ±0.02 ±0.03
G = 0.125, 8, 16 ±0.03 ±0.07
Differential gain drift G = 1, TA = –40°C to +125°C ±1 ppm/°C
G = 0.125, 0.25, 0.5, 2, 4, 8, 16, TA = –40°C to +125°C ±2
Differential gain nonlinearity G = 0.125 to 16, VOUTDIFF = 10 V 2 5 ppm
TA = –40°C to +125°C 10
OUTPUT
VOUT Output voltage No load VSOUT = ±2.25 V VLVSS + 0.1 VLVDD – 0.1 V
RL = 10 kΩ VSOUT = ±2.25 V VLVSS + 0.2 VLVDD – 0.2
VSOUT = ±18V VLVSS + 0.4 VLVDD – 0.4
CL Load capacitance  Stable operation for differential load 50 pF
ISC Short-circuit current Continuous to VSOUT / 2 ±45 mA
TA = –40°C to +125°C ±20 ±60
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 0.125 to 16 10 MHz
SR Slew rate G = 0.125 to 16, VOUTDIFF > 5 V 35 V/µs
tS Settling time G = 0.125 to 16
VINDIFF = 10-V step or VOUTDIFF = 10-V step		 To 0.01% 0.7 µs
To 0.0015% 0.95
Gain switching time 2 µs
THD+N Total harmonic distortion and Noise Differential input, f = 10 kHz, VO = 10 VPP –110 dB
Single-ended input, f = 10 kHz, VO = 10 VPP –105
HD2 Second-order harmonic distortion Differential input, f = 10 kHz, VO = 10 VPP –120 dB
Single-ended input, f = 10 kHz, VO = 10 VPP –110
HD3 Third-order harmonic distortion Differential input, f = 10 kHz, VO = 10 VPP –120 dB
Single-ended input, f = 10 kHz, VO = 10 VPP –110
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
VOCM Common-mode input voltage VS = ±4 V VLVSS + 1.5 VLVDD – 1.5 V
VS = ±18 V VLVSS + 2 VLVDD – 2
Small-signal bandwidth VOCM pin VOCM = 100 mVPP 16 MHz
Large-signal bandwidth VOCM pin VOCM = 0.6 VPP 16 MHz
DC output balance VOCM fixed at mid-supply (VO = ±1 V) 70 dB
Input impedance VVOCM pin 250 || 1 kΩ || pF
VOCM offset from mid-supply VOCM pin floating ±1 ±3.5 mV
VOCM offset voltage VOCM = VICM, VO = 0 V ±1 ±3.5 mV
VOCM offset voltage drift VOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±20 ±40 µV/°C
INPUT STAGE POWER SUPPLY
IQ_input Input stage quiescent current
VS+, VS–		 VIN = 0 V 3 3.7 mA
TA = –40°C to +125°C 4.5
OUTPUT STAGE POWER SUPPLY
IQ_output Output stage quiescent current
VLVDD, VLVSS		 VIN = 0 V, VOCM fixed at mid-supply 2.3 2.8 mA
TA = –40°C to 125°C 3.5
DIGITAL LOGIC
VIL Digital input logic low A0, A1, A2 pins, referred to DGND VDGND VDGND + 0.8 V
VIH Digital input logic high A0, A1, A2 pins, referred to DGND VDGND + 1.8 VS+ V
Digital input pin current A0, A1, A2 pins 1.5 3 µA
VDGND DGND voltage VS– (VS+) – 4 V
DGND reference current 4 10 µA