SBVS032I March   2002  – July 2022 REF3012 , REF3020 , REF3025 , REF3030 , REF3033 , REF3040

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply Voltage
      2. 8.3.2 Thermal Hysteresis
      3. 8.3.3 Temperature Drift
      4. 8.3.4 Noise Performance
      5. 8.3.5 Long-Term Stability
      6. 8.3.6 Load Regulation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Negative Reference Voltage
      2. 8.4.2 Data Acquisition
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

Figure 9-2 depicts a simplified schematic for this design showing the MSP430 ADC inputs and full input conditioning circuitry. The ADC is configured for a bipolar measurement where final conversion result is the differential voltage between the voltage at the positive and negative ADC inputs. The bipolar, GND-referenced input signal must be level-shifted and attenuated by the op amp so that the output is biased to VREF / 2 and has a differential voltage that is within the ±VREF / 2 input range of the ADC.