SBOS456H September   2008  – February 2015 REF5020A-Q1 , REF5025A-Q1 , REF5030A-Q1 , REF5040A-Q1 , REF5045A-Q1 , REF5050A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Per Device
    6. 7.6 Electrical Characteristics: All Devices
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply Voltage
      2. 8.3.2 Using the TRIM/NR Pin
      3. 8.3.3 Temperature Drift
      4. 8.3.4 Temperature Monitoring
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Thermal Hysteresis
    2. 9.2 Typical Applications
      1. 9.2.1 Standalone Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Dissipation
          2. 9.2.1.2.2 Noise Performance
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Negative-Reference Voltage Applications
      3. 9.2.3 Data-Acquisition Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Refer to Figure 33 and use the following guidelines for proper layout design:

  • Connect low-ESR, 0.1-μF ceramic bypass capacitors at the VIN and VOUT pins.
  • Decouple other active devices in the system per the device specifications.
  • Use a solid ground plane to help distribute heat and reduce electromagnetic-interference (EMI) noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Minimize trace length between the reference and bias connections to the end device to reduce noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible and only make perpendicular crossings when absolutely necessary.

11.2 Layout Example

REF5020A-Q1 REF5025A-Q1 REF5030A-Q1 REF5040A-Q1 REF5045A-Q1 REF5050A-Q1 layout_sbos456.gifFigure 33. REF50xxA-Q1 Layout Example