SLPS785 December   2023 RES11A

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching
      2. 7.3.2 Ratiometric Drift
      3. 7.3.3 Predictable Voltage Coefficient
      4. 7.3.4 Ultra-Low Noise
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Discrete Difference Amplifier
        1. 8.1.1.1 Difference-Amplifier Common-Mode Rejection Analysis
      2. 8.1.2 Discrete Instrumentation Amplifiers
        1. 8.1.2.1 Instrumentation Amplifier Common-Mode Rejection Analysis
      3. 8.1.3 Fully Differential Amplifier
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 TI Reference Designs
        4. 9.1.1.4 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDF|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

The design parameters are used with the aforementioned equations to select a nominal target G. When the possible VREF voltages available in the system are considered, VREF = 0 V with G = 9 is found to result in a VMID1 value of 1.8 V, well within the input common-mode range of a 3.3‑V rail-to-rail amplifier such as the OPA392. When the corresponding RES11A90 is employed, the loss terms ISTATIC1 and ISTATIC2 are nominally 1.80 mA and 1.77 mA for ILOAD = 300 mA, resulting in an effective floor of 1.77 mA for ILOAD. For simplicity, the error contributions of the INA stage VOS and IB are ignored.

For the INA stage, an integrated TI instrumentation amplifier (IA) can be used. Alternatively, a discrete approach can be implemented using another RES11A device or devices, and one or more op amps. For this example, an IA stage is constructed with two channels of a OPA4392 and a second RES11A90 (RIN3, RG3, RIN4, and RG4). This stage is in turn cascaded with a difference amplifier stage, constructed with the third amplifier channel and a RES11A00 (RIN5, RG5, RIN6, and RG6). The level-shifting stage gain of 10–1, multiplied by the instrumentation amplifier stage gain of 10, results in an effective unity-gain transfer function for VSHUNT. Therefore, the differential output voltage for this stage is approximately 0.3 V, with amplifier outputs of 1.936 V and 1.634 V. After the final difference amplifier stage gain of G = 10, the common-mode voltage drops out and the maximum value of the resulting VOUT is nominally 3.0 V, compatible with a single-ended 3.3‑V ADC such as the ADS7046. If desired, the fourth channel of the OPA4392 can be used to buffer this output signal and serve as a dedicated ADC driver.

GUID-20231002-SS0I-CK2X-LVLT-GD05GL9FG5VJ-low.svg Figure 8-7 High-Side Current Shunt Common-Mode Shifting Circuit