Table 5-1 Term Definitions

Table 5-2 User Address Map

Table 5-3 I²C Device Address

5.6.1 I²C Examples

Figure 5-4 and Figure 5-5 show examples of I²C accesses to the Control and Status registers, respectively. Comments are provided on the tags in the figures.

5.6.1.1 I²C Write

Figure 5-4 I²C Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x16 (RF Enable = 1)

A. I2C_READY signal, by being high indicates that I²C communication can be started.

B. The device address (18h because E0 = E1 = E2 = 0) is being transmitted out.

C. Register address is 0xFFFEh (which is the Control register).

D. I2C_READY line is now low, new I²C communication should not be started.

E. The data to write is transmitted (0016h).

5.6.1.2 I²C Read

Figure 5-5 I²C Access Example: Read of the Status Register at Address 0xFFFC, Responds With 0x00, 0x01 (Device_Ready = 1)

A. I2C_READY signal, by being high indicates that I²C communication can be started.

B. Packet has started: the device address (18h because E0 = E1 = E2 = 0) is being sent out.

C. Address FFFCh next is transmitted, which is the address of the status register.

D. An I²C restart was done and device address sent with a read selection.

E. Clock stretching is being used by the RF430CL331H when it needs more time to respond due to unfinished internal processing.

F. I2C_READY line is now low, new I²C communication should not be started.

G. RF430CL331H drives the SDA line and returns the value of the status register, which is 0001h.

H. I2C_READY signal has returned to high, indicating communication can be started. This occurs after a short period of time after a STOP condition (in square red). This brief time is necessary for the RF430CL331H to finish internal processing.

5.6.2 BIP-8 Communication Mode With I²C

The BIP-8 communication mode is enabled by setting the BIP-8 bit in the General Control register. All communication after setting this bit uses the following conventions with exactly 2 address bytes (16-bit address) and 2 data bytes (16-bit data) (see Table 5-4 and Table 5-5).

The Bit-Interleaved Parity (BIP-8) is calculated using 16-bit address and 16-bit data. If the received BIP-8 does not match with received data, no write is performed. The BIP-8 calculation does not include the I²C device address.

For read access, the Bit-Interleaved Parity (BIP-8) is calculated using the received 16-bit address and the 2 transmitted data bytes, and it is transmitted back to the master. The BIP-8 does not include the device address.

5.7.1 ISO/IEC 14443-3 Commands

These commands use the character, frame format, and timing that are described in ISO/IEC 14443-3, clause 7.1. The following commands are used to manage communication:

REQB and WUPB

The REQB and WUPB commands sent by the PCD are used to probe the field for PICCs of Type B. In addition, WUPB is used to wake up PICCs that are in the HALT state. The number of slots N is included in the command as a parameter to optimize the anticollision algorithm for a given application.

Slot-MARKER

After a REQB or WUPB command, the PCD may send up to (N – 1) Slot-MARKER commands to define the start of each timeslot. Slot-MARKER commands can be sent after the end of an ATQB message received by the PCD to mark the start of the next slot or earlier if no ATQB is received (no need to wait until the end of a slot, if this slot is known to be empty).

ATTRIB

The ATTRIB command sent by the PCD includes information required to select a single PICC. A PICC receiving an ATTRIB command with its identifier becomes selected and assigned to a dedicated channel. After being selected, this PICC only responds to commands defined in ISO/IEC 14443-4 that include its unique CID.

HLTB

The HLTB command is used to set a PICC in HALT state and stop responding to a REQB.

After answering to this command, the PICC ignores any commands except the WUPB.

5.7.2 NFC Tag Type 4 Commands

Select

Selection of applications or files

Read Binary

Read data from file

Update Binary

Update (erase and write) data to file

5.7.3 Data Rate Settings

The device supports data rates of 106, 212, 424, and 848 kbps.

The device always answers ATTRIB commands from the PCD that request higher data rates. The NFC Forum specifies for NFC-B a maximum data rate of 106 kbps. It is assumed that an NFC-compliant PCD would not request higher data rates, thus, no interoperability issues are expected.

Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD.

To change this behavior, follow these steps using the I²C serial interface:

1. If you do not want to support all data rates up to 848 kbps, change the Data Rate Capability byte according to Table 5-7. Table 5-6 summarizes how to write the data rate, and the Data Rate Capability byte is set by the DATA 0 value in Step 3. Write Access.
2. Do the steps of the selected sequence. It is important to execute this sequence (in Table 5-6) before setting the Control register.

NOTE

The General Control register (see Section 5.11.1) is set to 0 after the sequence is completed in Table 5-6.

Table 5-8 NDEF Application Data

Table 5-9 NDEF Application Data (Includes Proprietary Sections)

5.9.1 NDEF or Capability Container Select Procedure

This select procedure does not change between selection of the capability container or an NDEF file. These two types of selects can be differentiated by the file identifier that the RF430CL331H reports in the NDEF File Identifier register (see Section 5.11.7).

For the general flow, see Figure 5-7.

Figure 5-7 Select System Flow

The procedure:

1. PCD procedure:
   1. Issues a Capability Container or a NDEF File Select command.
2. RF430CL331H procedure:
   1. Receives the RF packet.
   2. Sets the NDEF File Identifier register (see Section 5.11.7) using the file identifier that was included in the packet from the PCD.
   3. Sets up the Status register (see Section 5.11.2) and the interrupt registers (see Section 5.11.3) to describe the file select request.
   4. Ensure that General Type 4 request interrupt is enabled to generate the required interrupt on the INTO pin.
3. Host controller procedure:
   1. Interrupt is received.
   2. Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
   3. The source of the interrupt is the General Type 4 request.
   4. When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read and the Type 4 Command field examined to determine what Type 4 command has been received.
   5. The result is a File Select command.
   6. The NDEF File Identifier register (see Section 5.11.7) should be read.
   7. The host controller should, search its available files and determine if the file exists.
   8. The interrupt must be cleared by writing to the Interrupt Flag register (see Section 5.11.3). This step must be done before setting the Interrupt Serviced field in the Host Response register (see Section 5.11.8).
   9. If a specific Status Word (SW) response is necessary (generally for communicating specific error conditions) to the Select command:
      1. Set the Custom Status Word Response register (see Section 5.11.13) with the desired status word.
      2. Set the Use Custom SW Response bit in the Host Response register (see Section 5.11.8).
   10. To complete servicing the Select command interrupt, set the Interrupt Serviced field in the Host Response register (see Section 5.11.8).

   Servicing of the Select command is complete.

4. RF430CL331H procedure:
   1. If the custom Status Words (SW) feature was not used:
      1. If the host controller indicated that the file existed, the response to the PCD is SW1 = 90h and SW2 = 00h.
      2. If the host controller indicated that the file did not exist, the response to the PCD is SW1 = 6Ah and SW2 = 82h.
   2. If the custom response feature was used, the response to the PCD is what was set in the Custom Status Word Response register (see Section 5.11.13).

5.9.2 NDEF or Capability Container Read Binary Procedure

This read procedure does not change between when the PCD reads the Capability Container or an NDEF file. These two types of reads can be differentiated by the file identifier that the RF430CL331H reports in the NDEF File Identifier register (see Section 5.11.7).

For the general flow, see Figure 5-8.

Figure 5-8 Read System Flow

The procedure:

1. PCD procedure:
   1. Issues a Capability Container or a NDEF Read Binary command.
2. RF430CL331H procedure:
   1. Receives the RF packet.
   2. Checks its buffer and determines if all of the requested data in the Read Binary command exists already in the buffer.
   3. If all the data is available in the buffer then (in the case that extra data was written in a previous read request):
      1. No interrupt is issued to the host controller.
      2. The data is supplied in the response packet to the PCD automatically.
      3. The status word response SW1 = 90h and SW2 = 00h is appended to the packet.
      4. The flow returns to wait for the next Type 4 request.
   4. If no data or only partial data is available, then an interrupt is issued to the host controller.
3. Host controller procedure:
   1. An interrupt is received.
   2. Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
   3. The source of the interrupt is the General Type 4 request.
   4. When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read and the Type 4 Command field examined to determine what Type 4 command has been received.
   5. The result is a Read Binary command.
   6. The NDEF File Identifier register (see Section 5.11.7) may be read, but it is not necessary as it is always the file that the last Select command selected.
   7. Read the Buffer Start register (see Section 5.11.11) to determine where in the buffer of the RF430CL331H to begin storing the data.
   8. Read the NDEF File Offset register (see Section 5.11.10) to determine at which index in the NDEF or CC file to begin supplying the data to the RF430CL331H.
   9. Read the NDEF Block Length register (see Section 5.11.9) to determine what block length the PCD is requesting.
   10. Check if the request is valid:
       1. If it is valid, write the data into the buffer of the RF430CL331H starting at Buffer Start index for NDEF Block Length bytes.
       2. If it is not valid, assert the Custom Status Word option in the Host Response register (see Section 5.11.8) and write the custom word in the Custom Status Word Response register (see Section 5.11.13). Only the status word response supplied will be sent out.
   11. If caching is desirable, extra sequential data can be written to the RF430CL331H buffer, up to the maximum RF430CL331H buffer length (length is 3000 bytes, highest index is 2999).

   NOTE

   To improve the Read Binary performance of the RF430CL331H , a caching feature may be used. After writing the requested Read Binary request data into the RF430CL331H buffer, extra sequential data may be written. If on the next Read Binary request, all of the requested data is in the buffer, the RF430CL331H automatically responds and services that request without any intervention of the host controller; that is, no interrupt is issued.

   12. Update the NDEF Block Length register (see Section 5.11.9) with the number of bytes written into the buffer.
   13. The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done before setting the Interrupt Serviced field in the Host Response register.
   14. To complete servicing the Read Binary command interrupt, set the Interrupt Serviced field in the Host Response register.
4. RF430CL331H procedure:
   1. Only the requested data (even if extra was supplied) is included in the response packet to the PCD. The status words are appended to the response packet per NFC Type 4 specification.
   2. If the command was valid, the status words are SW1 = 90h and SW2 = 00h.
   3. If the custom response feature was used, the response to the PCD is only what was set in the Custom Status Word Response register.

5.9.2.1 NDEF Read Command Internal Buffer Handling

Figure 5-9 Read Buffer Flow (no extra data)

In normal read mode, when Read Prefetch functionality has not been enabled, each Read Binary request that comes in, is passed to the host controller and the internal state machine is in blocking mode until the data is sent back to the RF430CL331H . The RF430CL331H uses the same memory for each request, it is no more than the size of the read request packet length.

5.9.2.2 NDEF Read Command Internal Buffer Handling (With Caching)

Figure 5-10 Read Buffer Flow (with caching)

1. PCD requests a block of data. PICC received the requests, sets up the internal register and asserts the INTO interrupt.
2. Host controller supplies the request but also adds more data on the file that is continuous with this request.
3. The next PCD request is fulfilled automatically because the data that is requested is already in the buffer. The host controller is not interrupted.
4. The next PCD request has insufficient data, so the data that is available is shifted to the beginning of the buffer and the unavailable data is requested.
5. The full request is transmitted out.
6. The cycle can repeat.

5.9.3 NDEF or Capability Container Read Procedure (Prefetch Feature)

The read prefetch feature includes the standard read procedure. However, after the requested data is written into the RF430CL331H buffer, when the RF430CL331H starts to transmit the requested data over the air, another interrupt is issued to the host controller indicating that extra data can be appended to the RF430CL331H buffer. The host controller can start adding data to the buffer while the RF430CL331H is transmitting over RF, because two tasks are happening at once, this increases the throughput of the system. For optimum operation, the host controller should cease to write extra data before the next interrupt. If the host controller does not cease to write, latency is introduced into the system, which can accumulate until requests start to time out. To determine how much is available to write the prefetch data, the time to send out the packet (that was requested) over RF can be calculated.

To enable read prefetch feature, the Read Prefetch interrupt must be enabled in the Interrupt Enable register (see Section 5.11.3).

For a general flow, see Figure 5-11.

Figure 5-11 Read System Flow (Prefetch Feature)

The procedure:

1. PCD procedure:
   1. Issues a Capability Container or a NDEF Read Binary command.
2. Dynamic Tag/RF430CL331H procedure:
   1. Receives the RF packet.
   2. Checks its buffer and determines if all of the requested data in the Read Binary command exists already in the buffer.
   3. If all the data is available in the buffer then (in the case that extra data was written in a previous read request)
      1. No General Type 4 interrupt is issued to the host controller.
      2. The data is supplied in the response packet to the PCD automatically.
      3. The status word response SW1 = 90h and SW2 = 00h is appended to the packet.
      4. The flow now goes to Step 4e.
   4. If no data or only partial data is available, then a General Type 4 interrupt is issued to the host controller.
3. Host controller procedure:
   1. Interrupt is received.
   2. Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
   3. The source of the interrupt is the General Type 4 request.
   4. When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read and the Type 4 Command field examined to determine what Type 4 command has been received.
   5. The result is a Read Binary command.
   6. The NDEF File Identifier register (see Section 5.11.7) may be read, but it is not necessary as it is always the file that the last Select command selected.
   7. Read the Buffer Start register (see Section 5.11.11) to determine where in the buffer of the RF430CL331H to begin storing the data.
   8. Read the NDEF File Offset register (see Section 5.11.10) to determine at which index in the NDEF or CC file to begin supplying the data to the RF430CL331H.
   9. Read the NDEF Block Length register (see Section 5.11.9) to determine what block length the PCD is requesting.
   10. Check if the request is valid:
       1. If it is valid write the data into the buffer of the RF430CL331H starting at Buffer Start index for NDEF Block Length bytes.
       2. If it is not valid, assert the Custom Status Word option in the Host Response register (see Section 5.11.8) and write the custom word in the Custom Status Word Response register (see Section 5.11.13). Only the status word response supplied will be sent out.
   11. Write the requested amount of data to the buffer starting at the Buffer Start register index.

   NOTE

   Read caching (writing data beyond the request in a General Type 4 request interrupt) should be avoided with the prefetch feature, because caching, at least initially, creates latency because the system is waiting (blocking) for the General Type 4 request interrupt to complete. Instead, in prefetch mode, only the requested data should be supplied in the General Type 4 request interrupt. When the Extra Data interrupt occurs afterwards (in tandem with the RF transmission), only then as much as possible extra data should be written to the buffer.

   12. Update the NDEF Block Length register with how much bytes were written into the buffer.
   13. The interrupt must be cleared by writing to the Interrupt Flag register. (This step must be done before setting the Interrupt Serviced field in the Host Response register.)
   14. To complete servicing the Read Binary command interrupt, set the Interrupt Serviced field in the Host Response register.
4. Dynamic Tag RF430CL331H procedure:
   1. Only the requested data (even if extra was supplied) is included in the response packet to the PCD. The status words are appended to the response packet per NFC Type 4 specification.
   2. If the command was valid, the status words are SW1 = 90h and SW2 = 00h.
   3. If the custom response feature was used, the response to the PCD is what was set in the Custom Status Word Response register.
   4. RF transmission starts, the Extra Data interrupt is always asserted.
5. The host controller must service the Extra Data interrupt by appending to the buffer extra sequential data up until the buffer size (3000 bytes).
   1. Checks the source of the interrupt by reading the interrupt registers.
   2. The interrupt is an Extra Data interrupt.
   3. Read the Buffer Start register to determine where in the buffer of the RF430CL331H to begin storing the data.

   NOTE

   When the Extra Data interrupt is enabled, the interrupt always occurs when the RF430CL331H is responding to the Read Binary request. However, this does not mean that every interrupt service can add to the RF430CL331H buffer (3000 bytes). If the Buffer Start register read indicates its index is at the end of the buffer, then no more data can be added. In this case the NDEF Block Length register should be set to 0 indicating that no data was added to the buffer. On the next Read Binary request, the valid data in the RF430CL331H buffer is shifted to the beginning to allow more room for extra data to be appended again.

   4. NDEF File Offset register can be read.
   5. Write sequential extra data to the buffer starting at the Buffer Start register index.
   6. The time limit of writing extra data to the buffer is until the next Read Binary command is completed to be transmitted to the RF430CL331H. After that point, latency starts to be introduced into the system as the processing of the new packet is delayed.
   7. Update the NDEF Block Length register with how many bytes were written into the buffer. If none, set to 0.
   8. The prefetch interrupt must be cleared by writing to the Interrupt Flag register.
   9. Set the Extra Data Send In bit in the Host Response register.
   10. This completes servicing of the Read Prefetch interrupt.

5.9.3.1 NDEF Read Command With Prefetch Internal Buffer Handling

Figure 5-12 Read Buffer Flow (Prefetch Feature)

The key feature with Prefetch is that while the Read Binary is being transmitted, the next packet can be sent out by the host controller and be filling the internal RF430CL331H buffer. Each request is stored in the subsequent buffer memory until the buffer limit is reached. When the buffer limit is reached, the remaining unsent data is shifted to the beginning of the buffer and what data is needed for the next request is requested (see Step 6). This command is requested using the General Type 4 request interrupt (not with a prefetch interrupt) because it does not happen during the time when the RF430CL331H is sending data over RF.

Read buffer flow procedure (see Figure 5-12):

1. PCD requests a block of data.
2. PICC received the requests, sets up the internal register and asserts the INTO interrupt.
3. Host services the interrupt by supplying the data. PICC transmits the data. After starting to transmit the data, PICC issues a Read Prefetch interrupt. The host supplies the extra data while the RF communication is ongoing.
4. When the next Read Binary request comes, because the data is already cached, only the Prefetch interrupt is asserted.
5. This time a Prefetch interrupt is asserted, but only a portion of the data can be written because the buffer space is running out.
6. Because there is not enough data to service the Read Binary requests, a General Type 4 interrupt is asserted. The partial data that has been written previously is shifted to the beginning of the buffer and the only the remaining missing data is requested in the interrupt.
7. The complete data is sent out. The cycle repeats (the Prefetch interrupt is issued again).

If a prefetch interrupt is issued for a file, but there is no more data to send, this interrupt can be canceled by servicing it by setting the data length sent to 0. Also if data was sent by a prefetch but it was not needed by the RF430CL331H (due to a different request by the PCD) that data is discarded and the new request handling initiated.

5.9.4 NDEF or Capability Container Write Procedure (Blocking)

This write procedure does not change between when the PCD writes the Capability Container or an NDEF file. These two types of writes can be differentiated by the file identifier that the RF430CL331H reports in the NDEF File Identifier register (see Section 5.11.7).

For a general flow, see Figure 5-13.

Figure 5-13 Write System Flow (Blocking)

The procedure:

1. PCD procedure:
   1. Issues a Capability Container or a NDEF File Write (or Update Binary) command.
2. RF430CL331H procedure:
   1. Receives the RF Update Binary packet.
   2. Sets up the appropriate registers.
   3. Issues the General Type 4 request interrupt.
3. Host controller procedure:
   1. Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
   2. The source of the interrupt is the General Type 4 request.
   3. When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read and the Type 4 Command field examined to determine what Type 4 command has been received.
   4. The result is an Update Binary command.
   5. The NDEF File Identifier register (see Section 5.11.7) may be read, but it is not necessary as it is always the file that the last Select command selected.
   6. Read the Buffer Start register (see Section 5.11.11) to determine where in the buffer of the RF430CL331H to begin reading the stored data. Reading this register is unnecessary as it is always 0.
   7. Read the NDEF File Offset register (see Section 5.11.10) to determine at which index of the NDEF or CC file the current data is starting.
   8. Read the NDEF Block Length register (see Section 5.11.9) to determine how much data is being sent by the PCD in this packet.
   9. Read the data from the buffer of the RF430CL331H starting at index of 0 until the block length supplied, updating the main file on the host controller.
   10. If a specific Status Word (SW) response is necessary to the Update Binary command:
       1. Set the Custom Status Word Response register (see Section 5.11.13) with the desired status word.
       2. Set the Use Custom SW Response bit in the Host Response register.
   11. The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done before setting the Interrupt Serviced field in the Host Response register.
   12. To complete servicing the Update Binary command interrupt, set the Interrupt Serviced field in the Host Response register.
4. RF430CL331H procedure:
   1. If the custom SW feature was not used, the response is status words SW1 = 90h and SW2 = 00h.
   2. If the custom response feature was used, the response to the PCD is what was set in the Custom Status Word Response register.

5.9.4.1 NDEF Write Command (Blocking) Internal Buffer Handling

Figure 5-14 Write Buffer Flow (Blocking)

The write with blocking stores the send in data packet until it is read out by the host controller. Once it has been read out, the next write data packet is stored in the same section of memory. The cycle repeats with more Update Binary packets.

5.9.5 NDEF or Capability Container Write Procedure (Nonblocking)

This command is different from the blocking operation in that the RF430CL331H automatically responds to an Update Binary command with a success acknowledgment upon receiving the Update Binary packet.

After the acknowledgment, the PCD starts to send the next Update Binary block. The intent is to increase throughput by downloading the previous Update Binary packet while the new one is being transmitted into a separate buffer on the RF430CL331H.

Care must be taken to read out the entire packet before the new one is completely transmitted to the RF430CL331H. Otherwise, this creates latency that, if not corrected, accumulates to the point where one Update Binary packet request eventually times out.

To enable write nonblocking mode, set the Automatic ACK On Write field in the General Control register.

For a general flow, see Figure 5-15.

Figure 5-15 Write System Flow (Nonblocking)

1. PCD procedure:
   1. Issues a Capability Container or a NDEF File Write (or Update Binary) command.
2. RF430CL331H procedure:
   1. Receives the RF Update Binary packet.
   2. Automatically responds with a successful acknowledgment: SW1 = 90h and SW2 = 00h.
   3. Sets up the appropriate registers.
   4. Issues the General Type 4 request interrupt.
   5. Waits for a new Update Binary packet to be transmitted to.
3. Host controller procedure:
   1. Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
   2. The source of the interrupt is the General Type 4 request.
   3. When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read and the Type 4 Command field examined to determine what Type 4 command has been received.
   4. The result is an Update Binary command.
   5. The NDEF File Identifier register (see Section 5.11.7) may be read, but it is not necessary as it is always the file that the last Select command selected.
   6. Read the Buffer Start register (see Section 5.11.11) to determine where in the buffer of the RF430CL331H to begin reading the stored data. Reading this register is unnecessary, as it is always 0.
   7. Read the NDEF File Offset register (see Section 5.11.10) to determine at which index of the NDEF or CC file the current data is starting.
   8. Read the NDEF Block Length register (see Section 5.11.9) to determine how much data is being sent by the PCD in this packet.
   9. Read the data from the buffer of the RF430CL331H, starting at the index of 0, until the block length supplied, updating the main file on the host controller.
   10. The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done before setting the Interrupt Serviced field in the Host Response register.
   11. To complete servicing the Update Binary command interrupt, set the Interrupt Serviced field in the Host Response register.

5.9.5.1 NDEF Write Procedure (Nonblocking) Internal Buffer Handling

Figure 5-16 Write System Flow (Nonblocking)

The main difference in a nonblocking write operation is that when the data packet has been received from the PCD, the host controller is reading out the packet while the next one is being sent in (see Steps 3 and 4 in Figure 5-16). Data is received into a temporary buffer and when the last packet has been read out, the data in the temporary buffer is copied into the standard buffer so the data can be accessed by the host controller.

5.11.1 General Control Register

5.11.2 Status Register

5.11.3 Interrupt Registers

The interrupt enable register (see Table 5-14 and Table 5-15) determines which interrupt events are signaled on the external output pin INTO. Setting any bit high in this register allows the corresponding event to trigger the interrupt signal. See Table 5-18 for a description of each interrupt.

All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO.

The interrupt flag register (see Table 5-16 and Table 5-17) is used to report the status of any interrupts that are pending. Setting any bit high in this register acknowledges and clears the interrupt associated with the respective bit. See Table 5-18 for a description of each interrupt.

5.11.4 CRC Registers

Writing the CRC address and the CRC length registers initiates a 16-bit CRC calculation of the specified address range. The length is always assumed to be even (16-bit aligned). Writing the length register starts the CRC calculation.

During the CRC calculation, the CRC active bit is set (= 1). When the calculation is complete, the CRC completion interrupt flag is set and the result of the CRC calculation can be read from the CRC result register. TI recommends performing a CRC calculation only when the RF interface is disabled (RF Enable = 0).

The CRC is calculated based on the CCITT polynomial initialized with 0xFFFF.

CCITT polynomial: x¹⁶ + x¹² + x⁵ + 1

5.11.5 Communication Watchdog Register

When the communication watchdog is enabled, it expects a write or read access within a specified period; otherwise, the watchdog resets the device. If the BIP-8 communication mode is enabled, the transfer must be valid to be accepted as a watchdog reset.

5.11.6 Version Register

Provides version information about the implemented ROM code.

5.11.7 NDEF File Identifier Register

This register is used by the host controller to determine which file has been selected (or also for Read Binary and Update Binary commands as needed).

5.11.8 Host Response Register

This register is used, after an interrupt is asserted by the RF430CL331H. It communicates various responses from the host controller. The actual interrupt flag clearing must happen immediately before setting the response in this register.

5.11.9 NDEF Block Length Register

This register indicates the block length of the Read Binary or Update Binary commands to the host controller.

5.11.10 NDEF File Offset Register

This register indicates the offset of the Read Binary or Update Binary commands to the host controller.

5.11.11 Buffer Start Register

This register is written after a Read Binary command by the host controller indicating the index in buffer memory where the data started to be written. On an Update Binary command, this register indicates where the RF430CL331H has started to write the packet in its buffer memory.

5.11.12 SWTX Register

When a PCD issues a command, there is a time-out that is negotiated (FWI in the SENSB_RES/ATQB command). The RF430CL331H has this amount of time to respond to the PCD command. If this time-out cannot be met by RF430CL331H, the NFC protocol allows a sending a S(WTX) request (refer to Section 13.2.2 of the NFC Digital Protocol). This allows the time-out to be restarted after the PCD S(WTX) response.

When the internal state machine determines that a wait time extension is necessary, it uses this register value to populate the INF field of the S(WTX) request (refer to Table 84 of the NFC Digital Protocol). This custom setting response allows flexibility in negotiating this wait time extension.

5.11.13 Custom Status Word Response Register

On a NFC Type 4 command (Select, Read Binary, Update Binary), the response contains a status word (SW).  This indicates whether or not the request was successful.  By default, the RF430CL331H handles the SW responses automatically with predefined values.  However, if custom responses are needed, for custom error status word responses, this feature may be used.

When the Use Custom SW Response is set in the Host Response register, the RF430CL331H firmware uses the SW set here to respond to the command.

5.12.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 7.2.1).

5.12.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 7.2.1).

5.12.3 JTAG Identification

This device does not provide JTAG-compliant boundary scan test.

5.12.4 Software Identification

The Version register (see Section 5.11.6) stores the software version number.