SLAS740A January   2013  – October 2015 RF430F5978

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics - Low-Power Mode Supply Currents
    8. 5.8  Thermal Resistance Characteristics
    9. 5.9  Digital Inputs
    10. 5.10 Digital Outputs
    11. 5.11 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    12. 5.12 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency Mode
    14. 5.14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    15. 5.15 Internal Reference, Low-Frequency Oscillator (REFO)
    16. 5.16 DCO Frequency
    17. 5.17 PMM, Brown-Out Reset (BOR)
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS High Side
    20. 5.20 PMM, SVM High Side
    21. 5.21 PMM, SVS Low Side
    22. 5.22 PMM, SVM Low Side
    23. 5.23 Wake-up Times From Low-Power Modes and Reset
    24. 5.24 Timer_A
    25. 5.25 USCI (UART Mode) Clock Frequency
    26. 5.26 USCI (UART Mode)
    27. 5.27 USCI (SPI Master Mode) Clock Frequency
    28. 5.28 USCI (SPI Master Mode)
    29. 5.29 USCI (SPI Slave Mode)
    30. 5.30 USCI (I2C Mode)
    31. 5.31 12-Bit ADC, Power Supply and Input Range Conditions
    32. 5.32 12-Bit ADC, Timing Parameters
    33. 5.33 12-Bit ADC, Linearity Parameters
    34. 5.34 12-Bit ADC, Temperature Sensor and Built-In VMID
    35. 5.35 REF, External Reference
    36. 5.36 REF, Built-In Reference
    37. 5.37 Comparator B
    38. 5.38 Flash Memory
    39. 5.39 JTAG and Spy-Bi-Wire Interface
    40. 5.40 RF1A CC1101 Radio Parameters
      1. 5.40.1  RF Crystal Oscillator, XT2
      2. 5.40.2  Current Consumption, Reduced-Power Modes
      3. 5.40.3  Current Consumption, Receive Mode
      4. 5.40.4  Current Consumption, Transmit Mode
      5. 5.40.5  Typical TX Current Consumption, 315 MHz
      6. 5.40.6  Typical TX Current Consumption, 433 MHz
      7. 5.40.7  Typical TX Current Consumption, 868 MHz
      8. 5.40.8  Typical TX Current Consumption, 915 MHz
      9. 5.40.9  RF Receive, Overall
      10. 5.40.10 RF Receive, 315 MHz
      11. 5.40.11 RF Receive, 433 MHz
      12. 5.40.12 RF Receive, 868 or 915 MHz
      13. 5.40.13 Typical Sensitivity, 315 MHz, Sensitivity-Optimized Setting
      14. 5.40.14 Typical Sensitivity, 433 MHz, Sensitivity-Optimized Setting
      15. 5.40.15 Typical Sensitivity, 868 MHz, Sensitivity-Optimized Setting
      16. 5.40.16 Typical Sensitivity, 915 MHz, Sensitivity-Optimized Setting
      17. 5.40.17 RF Transmit
      18. 5.40.18 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
      19. 5.40.19 Typical Output Power, 315 MHz
      20. 5.40.20 Typical Output Power, 433 MHz
      21. 5.40.21 Typical Output Power, 868 MHz
      22. 5.40.22 Typical Output Power, 915 MHz
      23. 5.40.23 Frequency Synthesizer Characteristics
      24. 5.40.24 Typical RSSI_offset Values
    41. 5.41 3D LF Front-End Parameters
      1. 5.41.1 Recommended Operating Conditions
      2. 5.41.2 Resonant Circuits - LF Front End
      3. 5.41.3 External Antenna Coil - LF Front End
      4. 5.41.4 Resonant Circuit Capacitor - LF Front End
      5. 5.41.5 Charge Capacitor - LF Front End
      6. 5.41.6 LF Wake Receiver Electrical Characteristics
      7. 5.41.7 RSSI - LF Wake Receiver Electrical Characteristics
  6. 6Detailed Description
    1. 6.1  3D LF Wake Receiver and 3D Transponder Interface
      1. 6.1.1 3D LF Front End
      2. 6.1.2 EEPROM
      3. 6.1.3 Switch Interface
    2. 6.2  Sub-1-GHz Radio
    3. 6.3  CPU
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power-Management Module (PMM)
      3. 6.11.3  Digital I/O
      4. 6.11.4  Port Mapping Controller
      5. 6.11.5  System (SYS) Module
      6. 6.11.6  DMA Controller
      7. 6.11.7  Watchdog Timer (WDT_A)
      8. 6.11.8  CRC16
      9. 6.11.9  Hardware Multiplier
      10. 6.11.10 AES128 Accelerator
      11. 6.11.11 Universal Serial Communication Interface (USCI)
      12. 6.11.12 TA0
      13. 6.11.13 TA1
      14. 6.11.14 Real-Time Clock (RTC_A)
      15. 6.11.15 REF Voltage Reference
      16. 6.11.16 Comparator_B
      17. 6.11.17 ADC12_A
      18. 6.11.18 Embedded Emulation Module (EEM) (S Version)
      19. 6.11.19 Peripheral File Map
    12. 6.12 Input/Output Schematics
      1. 6.12.1  Port P1, P1.0 to P1.4, Input/Output With Schmitt Trigger
      2. 6.12.2  Port P1, P1.5 to P1.7, Input/Output With Schmitt Trigger
      3. 6.12.3  Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
      4. 6.12.4  Port P2, P2.4 and P2.5, Input/Output With Schmitt Trigger
      5. 6.12.5  Port P3, P3.1 to P3.3, P3.5, and P3.7, Input/Output With Schmitt Trigger
      6. 6.12.6  Port P4, P4.0 to P4.2, Input/Output With Schmitt Trigger
      7. 6.12.7  Port P5, P5.0, Input/Output With Schmitt Trigger
      8. 6.12.8  Port P5, P5.1, Input/Output With Schmitt Trigger
      9. 6.12.9  Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      10. 6.12.10 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptor Structures
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Circuit
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Getting Started and Next Steps
      2. 8.1.2 Device and Development Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Export Control Notice
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Characteristics

Table 3-1 summarizes the device characteristics.

Table 3-1 Family Members

DEVICE PROGRAM (KB) SRAM (KB) EEPROM (Byte) Timer_A (1) LF INTERFACE USCI ADC12_A CHANNELS Comp_B CHANNELS I/O PACKAGE
TRANSPONDER CHANNELS WAKE RECEIVER CHANNELS CHANNEL A:
UART, LIN, IrDA, SPI		 CHANNEL B:
SPI, I2C
RF430F5978 32 4 1776 5, 3 3 3 1 1 8 ext, 4 int 8 27 64 RGC
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 5, 3 would represent two instantiations of Timer_A, the first instantiation having 5 and the second instantiation having 3 capture compare registers and PWM output generators, respectively.