SPNS180B September   2012  – June 2015 RM42L432

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Terminal Functions
      1. 4.2.1  High-End Timer (N2HET)
      2. 4.2.2  Enhanced Quadrature Encoder Pulse Modules (eQEP)
      3. 4.2.3  General-Purpose Input/Output (GPIO)
      4. 4.2.4  Controller Area Network Interface Modules (DCAN1, DCAN2)
      5. 4.2.5  Multibuffered Serial Peripheral Interface (MibSPI1)
      6. 4.2.6  Standard Serial Peripheral Interface (SPI2)
      7. 4.2.7  Local Interconnect Network Controller (LIN)
      8. 4.2.8  Multibuffered Analog-to-Digital Converter (MibADC)
      9. 4.2.9  System Module
      10. 4.2.10 Error Signaling Module (ESM)
      11. 4.2.11 Main Oscillator
      12. 4.2.12 Test/Debug Interface
      13. 4.2.13 Flash
      14. 4.2.14 Core Supply
      15. 4.2.15 I/O Supply
      16. 4.2.16 Core and I/O Supply Ground Reference
    3. 4.3 Output Multiplexing and Control
      1. 4.3.1 Notes on Output Multiplexing
      2. 4.3.2 General Rules for Multiplexing Control Registers
    4. 4.4 Special Multiplexed Options
      1. 4.4.1 Filtering for eQEP Inputs
        1. 4.4.1.1 eQEPA Input
        2. 4.4.1.2 eQEPB Input
        3. 4.4.1.3 eQEPI Input
        4. 4.4.1.4 eQEPS Input
      2. 4.4.2 N2HET PIN_nDISABLE Input Port
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Thermal Resistance Characteristics for PZ
    9. 5.9  Input/Output Electrical Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
  6. 6System Information and Electrical Specifications
    1. 6.1  Voltage Monitor Characteristics
      1. 6.1.1 Important Considerations
      2. 6.1.2 Voltage Monitor Operation
      3. 6.1.3 Supply Filtering
    2. 6.2  Power Sequencing and Power-On Reset
      1. 6.2.1 Power-Up Sequence
      2. 6.2.2 Power-Down Sequence
      3. 6.2.3 Power-On Reset: nPORRST
        1. 6.2.3.1 nPORRST Electrical and Timing Requirements
    3. 6.3  Warm Reset (nRST)
      1. 6.3.1 Causes of Warm Reset
      2. 6.3.2 nRST Timing Requirements
    4. 6.4  ARM Cortex-R4 CPU Information
      1. 6.4.1 Summary of ARM Cortex-R4 CPU Features
      2. 6.4.2 ARM Cortex-R4 CPU Features Enabled by Software
      3. 6.4.3 Dual Core Implementation
      4. 6.4.4 Duplicate clock tree after GCLK
      5. 6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety
      6. 6.4.6 CPU Self-Test
        1. 6.4.6.1 Application Sequence for CPU Self-Test
        2. 6.4.6.2 CPU Self-Test Clock Configuration
        3. 6.4.6.3 CPU Self-Test Coverage
    5. 6.5  Clocks
      1. 6.5.1 Clock Sources
        1. 6.5.1.1 Main Oscillator
          1. 6.5.1.1.1 Timing Requirements for Main Oscillator
        2. 6.5.1.2 Low-Power Oscillator
          1. 6.5.1.2.1 Features
          2. 6.5.1.2.2 LPO Electrical and Timing Specifications
        3. 6.5.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.5.1.3.1 Block Diagram
          2. 6.5.1.3.2 PLL Timing Specifications
      2. 6.5.2 Clock Domains
        1. 6.5.2.1 Clock Domain Descriptions
        2. 6.5.2.2 Mapping of Clock Domains to Device Modules
      3. 6.5.3 Clock Test Mode
    6. 6.6  Clock Monitoring
      1. 6.6.1 Clock Monitor Timings
      2. 6.6.2 External Clock (ECLK) Output Functionality
      3. 6.6.3 Dual Clock Comparator
        1. 6.6.3.1 Features
        2. 6.6.3.2 Mapping of DCC Clock Source Inputs
    7. 6.7  Glitch Filters
    8. 6.8  Device Memory Map
      1. 6.8.1 Memory Map Diagram
      2. 6.8.2 Memory Map Table
      3. 6.8.3 Master/Slave Access Privileges
    9. 6.9  Flash Memory
      1. 6.9.1 Flash Memory Configuration
      2. 6.9.2 Main Features of Flash Module
      3. 6.9.3 ECC Protection for Flash Accesses
      4. 6.9.4 Flash Access Speeds
    10. 6.10 Flash Program and Erase Timings for Program Flash
    11. 6.11 Flash Program and Erase Timings for Data Flash
    12. 6.12 Tightly Coupled RAM Interface Module
      1. 6.12.1 Features
      2. 6.12.2 TCRAMW ECC Support
    13. 6.13 Parity Protection for Accesses to peripheral RAMs
    14. 6.14 On-Chip SRAM Initialization and Testing
      1. 6.14.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.14.1.1 Features
        2. 6.14.1.2 PBIST RAM Groups
      2. 6.14.2 On-Chip SRAM Auto Initialization
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
    17. 6.17 Error Signaling Module
      1. 6.17.1 Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset / Abort / Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 MIBADC Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4 Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET Checking
        1. 7.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)
      5. 7.4.5 Disabling N2HET Outputs
      6. 7.4.6 High-End Timer Transfer Unit (N2HET)
        1. 7.4.6.1 Features
        2. 7.4.6.2 Trigger Connections
    5. 7.5 Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6 Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7 Multibuffered / Standard Serial Peripheral Interface
      1. 7.7.1 Features
      2. 7.7.2 MibSPI Transmit and Receive RAM Organization
      3. 7.7.3 MibSPI Transmit Trigger Events
        1. 7.7.3.1 MIBSPI1 Event Trigger Hookup
      4. 7.7.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.7.5 SPI Slave Mode I/O Timings
    8. 7.8 Enhanced Quadrature Encoder (eQEP)
      1. 7.8.1 Clock Enable Control for eQEPx Modules
      2. 7.8.2 Using eQEPx Phase Error
      3. 7.8.3 Input Connections to eQEPx Modules
      4. 7.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Getting Started
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
    7. 8.7 Device Identification Code Register
    8. 8.8 Die Identification Registers
    9. 8.9 Module Certifications
      1. 8.9.1 DCAN Certification
      2. 8.9.2 LIN Certifications
        1. 8.9.2.1 LIN Master Mode
        2. 8.9.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.9.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Addendum
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 PZ QFP Package Pinout (100-Pin)

Figure 4-1 shows the 100-pin PZ QFP package pinout.

RM42L432 pz_100_pin_f3.gifFigure 4-1 PZ QFP Package Pinout (100-Pin)

Note: Pins can have multiplexed functions. Only the default function is depicted in Figure 4-1.

4.2 Terminal Functions

Table 4-1 through Table 4-16 identify the external signal names, the associated pin numbers along with the mechanical package designator, the pin type (Input, Output, I/O, Power, or Ground), whether the pin has any internal pullup/pulldown, whether the pin can be configured as a GPIO, and a functional pin description.

NOTE

In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.


All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.


All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.

4.2.1 High-End Timer (N2HET)

Table 4-1 High-End Timer (N2HET)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
N2HET[0] 19 I/O Pulldown Programmable, 20 µA Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GPIO).
Each terminal has a suppression filter with a programmable duration.
N2HET[2] 22
N2HET[4] 25
N2HET[6] 26
N2HET[8] 74
N2HET[10] 83
N2HET[12] 89
N2HET[14] 90
N2HET[16] 97
MIBSPI1nCS[1]/EQEPS/
N2HET[17]		 93
N2HET[18] 98
MIBSPI1nCS[2]/N2HET[20]/
N2HET[19] 		27
MIBSPI1nCS[2]/N2HET[20]/
N2HET[19]		 27
N2HET[22] 11
N2HET[24] 64
MIBSPI1nCS[3]/N2HET[26] 39
ADEVT/N2HET[28] 58
GIOA[7]/N2HET[29] 18
MIBSPI1nENA/N2HET[23]/
N2HET[30]		 68
GIOA[6]/SPI2nCS[1]/N2HET[31] 12

4.2.2 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-2 Enhanced Quadrature Encoder Pulse Modules (eQEP)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
SPI3CLK/EQEPA 36 Input Pullup Fixed 20 µA Enhanced QEP Input A
SPI3nENA/EQEPB 37 Input Enhanced QEP Input B
SPI3nCS[0]/EQEPI 38 I/O Enhanced QEP Index
MIBSPI1nCS[1]/EQEPS/N2HET[17] 93 I/O Enhanced QEP Strobe

4.2.3 General-Purpose Input/Output (GPIO)

Table 4-3 General-Purpose Input/Output (GPIO)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
GIOA[0]/SPI3nCS[3] 1 I/O Pulldown Programmable, 20 µA General-purpose input/output
All GPIO terminals can generate interrupts to the CPU on rising/falling/both edges.
GIOA[1]/SPI3nCS[2] 2
GIOA[2]/SPI3nCS[1] 5
GIOA[3]/SPI2nCS[3] 8
GIOA[4]/SPI2nCS[2] 9
GIOA[5]/EXTCLKIN 10
GIOA[6]/SPI2nCS[1]/N2HET[31] 12
GIOA[7]/N2HET[29] 18

4.2.4 Controller Area Network Interface Modules (DCAN1, DCAN2)

Table 4-4 Controller Area Network Interface Modules (DCAN1, DCAN2)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
CAN1RX 63 I/O Pullup Programmable, 20 µA CAN1 Receive, or general-purpose I/O (GPIO)
CAN1TX 62 CAN1 Transmit, or GPIO
CAN2RX 92 CAN2 Receive, or GPIO
CAN2TX 91 CAN2 Transmit, or GPIO

4.2.5 Multibuffered Serial Peripheral Interface (MibSPI1)

Table 4-5 Multibuffered Serial Peripheral Interface (MibSPI1)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
MIBSPI1CLK 67 I/O Pullup Programmable, 20 µA MibSPI1 Serial Clock, or GPIO
MIBSPI1nCS[0] 73 MibSPI1 Chip Select, or GPIO
MIBSPI1nCS[1]/EQEPS/N2HET[17] 93
MIBSPI1nCS[2]/N2HET[20]/N2HET[19] 27
MIBSPI1nCS[3]/N2HET[26] 39
MIBSPI1nENA/N2HET[23]/N2HET[30] 68 MibSPI1 Enable, or GPIO
MIBSPI1SIMO 65 MibSPI1 Slave-In-Master-Out, or GPIO
MIBSPI1SOMI 66 MibSPI1 Slave-Out-Master-In, or GPIO

4.2.6 Standard Serial Peripheral Interface (SPI2)

Table 4-6 Standard Serial Peripheral Interface (SPI2)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
SPI2CLK 71 I/O Pullup Programmable, 20 µA SPI2 Serial Clock, or GPIO
SPI2nCS[0] 23 SPI2 Chip Select, or GPIO
GIOA[6]/SPI2nCS[1]/N2HET[31] 12
GIOA[4]/SPI2nCS[2] 9
GIOA[3]/SPI2nCS[3] 8
SPI2SIMO 70 SPI2 Slave-In-Master-Out, or GPIO
SPI2SOMI 69 SPI2 Slave-Out-Master-In, or GPIO
The drive strengths for the SPI2CLK, SPI2SIMO, and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register fo SPI2.
SRS = 0 for 8-mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0.
SRS = 1 for 2-mA drive (slow)
SPI3CLK/EQEPA 36 I/O Pullup Programmable, 20 µA SPI3 Serial Clock, or GPIO
SPI3nCS[0]/EQEPI 38 SPI3 Chip Select, or GPIO
GIOA[2]/SPI3nCS[1] 5
GIOA[1]/SPI3nCS[2] 2
GIOA[0]/SPI3nCS[3] 1
SPI3nENA/EQEPB 37 SPI3 Enable, or GPIO
SPI3SIMO 35 SPI3 Slave-In-Master-Out, or GPIO
SPI3SOMI 34 SPI3 Slave-Out-Master-In, or GPIO

4.2.7 Local Interconnect Network Controller (LIN)

Table 4-7 Local Interconnect Network Controller (LIN)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
LINRX 94 I/O Pullup Programmable, 20 µA LIN Receive, or GPIO
LINTX 95 LIN Transmit, or GPIO

4.2.8 Multibuffered Analog-to-Digital Converter (MibADC)

Table 4-8 Multibuffered Analog-to-Digital Converter (MibADC)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
ADEVT/N2HET[28] 58 I/O Pullup Programmable, 20 µA ADC event trigger or GPIO
ADIN[0] 42 Input N/A None Analog inputs
ADIN[1] 49
ADIN[2] 51
ADIN[3] 52
ADIN[4] 54
ADIN[5] 55
ADIN[6] 56
ADIN[7] 43
ADIN[8] 57
ADIN[9] 48
ADIN[10] 50
ADIN[11] 53
ADIN[16] 40
ADIN[17] 41
ADIN[20] 44
ADIN[21] 45
VCCAD/ADREFHI 46 Input/Power N/A None ADC high reference level/ADC operating supply
VSSAD/ADREFLO 47 Input/Ground N/A None ADC low reference level/ADC supply ground

4.2.9 System Module

Table 4-9 System Module

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
ECLK 84 I/O Pulldown Programmable, 20 µA External prescaled clock output, or GPIO.
GIOA[5]/EXTCLKIN 10 Input Pulldown 20 µA External Clock In
nPORRST 31 Input Pulldown 100 µA Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter.
nRST 81 I/O Pullup 100 µA The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter.

4.2.10 Error Signaling Module (ESM)

Table 4-10 Error Signaling Module (ESM)

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
nERROR 82 I/O Pulldown 20 µA ESM error signal. Indicates error of high severity.

4.2.11 Main Oscillator

Table 4-11 Main Oscillator

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
OSCIN 14 Input N/A None From external crystal/resonator, or external clock input
OSCOUT 16 Output N/A None To external crystal/resonator
KELVIN_GND 15 Input N/A None Dedicated ground for oscillator

4.2.12 Test/Debug Interface

Table 4-12 Test/Debug Interface

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
nTRST 76 Input Pulldown Fixed, 100 µA JTAG test hardware reset
RTCK 80 Output N/A None JTAG return test clock
TCK 79 Input Pulldown Fixed, 100 µA JTAG test clock
TDI 77 I/O Pullup Fixed, 100 µA JTAG test data in
TDO 78 Output Fixed, 100-µA Pulldown None JTAG test data out
TMS 75 I/O Pullup Fixed, 100 µA JTAG test select
TEST 24 I/O Pulldown Fixed, 100 µA Test enable. This terminal must be connected to ground directly or through a pulldown resistor.

4.2.13 Flash

Table 4-13 Flash

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
FLTP1 3 Input N/A None Flash test pins. For proper operation this terminal must connect only to a test pad or not be connected at all [no connect (NC)].
The test pad must not be exposed in the final product where it might be subjected to an ESD event.
FLTP2 4 Input N/A None
VCCP 96 3.3-V Power N/A None Flash external pump voltage (3.3 V). This terminal is required for both flash read and flash program and erase operations.

4.2.14 Core Supply

Table 4-14 Core Supply

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
VCC 13 1.2-V Power N/A None Digital logic and RAM supply
VCC 21
VCC 30
VCC 32
VCC 61
VCC 88
VCC 99

4.2.15 I/O Supply

Table 4-15 I/O Supply

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
VCCIO 6 3.3-V Power N/A None I/O supply
VCCIO 28
VCCIO 60
VCCIO 85

4.2.16 Core and I/O Supply Ground Reference

Table 4-16 Core and I/O Supply Ground Reference

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 100 PZ
VSS 7 Ground N/A None Device Ground Reference. This is a single ground reference for all supplies except for the ADC supply.
VSS 17
VSS 20
VSS 29
VSS 33
VSS 59
VSS 72
VSS 86
VSS 87
VSS 100

4.3 Output Multiplexing and Control

Output multiplexing will be used in the device. The multiplexing is used to allow development of additional package and feature combinations as well as to maintain pinout compatibility with the marketing device family.

In all cases indicated as multiplexed, the output buffers are multiplexed.

4.3.1 Notes on Output Multiplexing

Table 4-17 shows the output signal multiplexing and control signals for selecting the desired functionality for each pin.

  • The pins default to the signal defined by the DEFAULT FUNCTION column in Table 4-17
  • The CONTROL 1, CONTROL 2, and CONTROL 3 columns indicate the multiplexing control register and the bit that must be set in order to select the corresponding functionality to be output on any particular pin.

    • For example, consider the multiplexing on pin 18, shown in Table 4-18 .

    Table 4-17 Output Mux Options

    100 PZ PIN DEFAULT
    FUNCTION    		 CONTROL 1 OPTION2 CONTROL 2 OPTION 3 CONTROL 3
    1 GIOA[0] PINMMR0[8] SPI3nCS[3] PINMMR0[9] – –
    2 GIOA[1] PINMMR1[0] SPI3nCS[2] PINMMR1[1] – –
    5 GIOA[2] PINMMR1[8] SPI3nCS[1] PINMMR1[9] – –
    8 GIOA[3] PINMMR1[16] SPI2nCS[3] PINMMR1[17] – –
    9 GIOA[4] PINMMR1[24] SPI2nCS[2] PINMMR1[25] – –
    10 GIOA[5] PINMMR2[0] EXTCLKIN PINMMR2[1] – –
    12 GIOA[6] PINMMR2[8] SPI2nCS[1] PINMMR2[9] N2HET[31] PINMMR2[10]
    18 GIOA[7] PINMMR2[16] N2HET[29] PINMMR2[17] – –
    93 MIBSPI1nCS[1] PINMMR6[8] EQEPS PINMMR6[9] N2HET[17] PINMMR6[10]
    27 MIBSPI1nCS[2] PINMMR3[0] N2HET[20] PINMMR3[1] N2HET[19] PINMMR3[2]
    39 MIBSPI1nCS[3] PINMMR4[8] N2HET[26] PINMMR4[9] – –
    68 MIBSPI1nENA PINMMR5[8] N2HET[23] PINMMR5[9] N2HET[30] PINMMR5[10]
    36 SPI3CLK PINMMR3[16] EQEPA PINMMR3[17] – –
    38 SPI3nCS[0] PINMMR4[0] EQEPI PINMMR4[1] – –
    37 SPI3nENA PINMMR3[24] EQEPB PINMMR3[25] – –
    58 ADEVT PINMMR4[16] N2HET[28] PINMMR4[17] – –

    Table 4-18 Muxing Example

    100 PZ PIN DEFAULT
    FUNCTION    		 CONTROL 1 OPTION2 CONTROL 2 OPTION 3 CONTROL 3
    18 GIOA[7] PINMMR2[16] N2HET[29] PINMMR2[17] – –
  • When GIOA[7] is configured as an output pin in the GPIO module control register, then the programmed output level appears on pin 18 by default. The PINMMR2[16] bit is set by default to indicate that the GIOA[7] signal is selected to be output.
  • If the application must output the N2HET[29] signal on pin 18, it must clear PINMMR2[16] and set PINMMR2[17].
  • The pin is connected as input to both the GPIO and N2HET modules. That is, there is no input multiplexing on this pin.

4.3.2 General Rules for Multiplexing Control Registers

  • The PINMMR control registers can only be written in privileged mode. A write in a nonprivileged mode will generate an error response.
  • If the application writes all 0s to any PINMMR control register, then the default functions are selected for the affected pins.
  • Each byte in a PINMMR control register is used to select the functionality for a given pin. If the application sets more than 1 bit within a byte for any pin, then the default function is selected for this pin.
  • Some bits within the PINMMR registers could be associated with internal pads that are not brought out in the 100-pin package. As a result, bits marked reserved should not be written as 1.

4.4 Special Multiplexed Options

Special controls are implemented to affect particular functions on this microcontroller. These controls are described in this section.

4.4.1 Filtering for eQEP Inputs

4.4.1.1 eQEPA Input

  • When PINMMR8[0] = 1, the eQEPA input is double-synchronized using VCLK.
  • When PINMMR8[0] = 0 and PINMMR8[1] = 1, the eQEPA input is double-synchronized and then qualified through a fixed 6-bit counter using VCLK.
  • PINMMR8[0] = 0 and PINMMR8[1] = 0 is an illegal combination and behavior defaults to PINMMR8[0] = 1.

4.4.1.2 eQEPB Input

  • When PINMMR8[8] = 1, the eQEPB input is double-synchronized using VCLK.
  • When PINMMR8[8] = 0 and PINMMR8[9] = 1, the eQEPB input is double-synchronized and then qualified through a fixed 6-bit counter using VCLK.
  • PINMMR8[8] = 0 and PINMMR8[9] = 0 is an illegal combination and behavior defaults to PINMMR8[8] = 1.

4.4.1.3 eQEPI Input

  • When PINMMR8[16] = 1, the eQEPI input is double-synchronized using VCLK.
  • When PINMMR8[16] = 0 and PINMMR8[17] = 1, the eQEPI input is double-synchronized and then qualified through a fixed 6-bit counter using VCLK.
  • PINMMR8[16] = 0 and PINMMR8[17] = 0 is an illegal combination and behavior defaults to PINMMR8[16] = 1.

4.4.1.4 eQEPS Input

  • When PINMMR8[24] = 1, the eQEPS input is double-synchronized using VCLK.
  • When PINMMR8[24] = 0 and PINMMR8[25] = 1, the eQEPS input is double-synchronized and then qualified through a fixed 6-bit counter using VCLK.
  • PINMMR8[24] = 0 and PINMMR8[25] = 0 is an illegal combination and behavior defaults to PINMMR8[24] = 1.

4.4.2 N2HET PIN_nDISABLE Input Port

  • When PINMMR9[0] = 1, GIOA[5] is connected directly to N2HET PIN_nDISABLE input of the N2HET module.
  • When PINMMR9[0] = 0 and PINMMR9[1] = 1, EQEPERR is inverted and double-synchronized using VCLK before connecting directly to the N2HET PIN_nDISABLE input of the N2HET module.
  • PINMMR9[0] = 0 and PINMMR9[1] = 0 is an illegal combination and behavior defaults to PINMMR9[0] = 1.