SPNS229C October   2014  – November 2016 RM44L520 , RM44L920

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 PGE QFP Package Pinout (144-Pin)
      2. 4.1.2 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Signal Descriptions
      1. 4.2.1 PGE Package Terminal Functions
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.2.1.3  Enhanced Capture Modules (eCAP)
        4. 4.2.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.2.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.2.1.6  General-Purpose Input/Output (GIO)
        7. 4.2.1.7  Controller Area Network Controllers (DCAN)
        8. 4.2.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.2.1.9  Standard Serial Communication Interface (SCI)
        10. 4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.2.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.2.1.13 System Module Interface
        14. 4.2.1.14 Clock Inputs and Outputs
        15. 4.2.1.15 Test and Debug Modules Interface
        16. 4.2.1.16 Flash Supply and Test Pads
        17. 4.2.1.17 Supply for Core Logic: 1.2V nominal
        18. 4.2.1.18 Supply for I/O Cells: 3.3V nominal
        19. 4.2.1.19 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 PZ Package Terminal Functions
        1. 4.2.2.1  High-End Timer (N2HET) Modules
        2. 4.2.2.2  Enhanced Capture Modules (eCAP)
        3. 4.2.2.3  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        4. 4.2.2.4  Enhanced Pulse-Width Modulator Modules (ePWM)
        5. 4.2.2.5  General-Purpose Input/Output (GIO)
        6. 4.2.2.6  Controller Area Network Interface Modules (DCAN1, DCAN2)
        7. 4.2.2.7  Standard Serial Peripheral Interfaces (SPI2 and SPI4)
        8. 4.2.2.8  Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
        9. 4.2.2.9  Local Interconnect Network Controller (LIN)
        10. 4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
        11. 4.2.2.11 System Module Interface
        12. 4.2.2.12 Clock Inputs and Outputs
        13. 4.2.2.13 Test and Debug Modules Interface
        14. 4.2.2.14 Flash Supply and Test Pads
        15. 4.2.2.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.2.2.17 Ground Reference for All Supplies Except VCCAD
    3. 4.3 Pin Multiplexing
      1. 4.3.1 Output Multiplexing
      2. 4.3.2 Multiplexing of Inputs
    4. 4.4 Buffer Type
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions
    6. 5.6 Power Consumption Over Recommended Operating Conditions
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 SYSCLK (Frequencies)
        1. 5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains
        2. 5.8.1.2 Wait States Required - PGE and PZ Packages
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Module
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 Vectored Interrupt Manager
      1. 6.14.1 VIM Features
      2. 6.14.2 Interrupt Request Assignments
    15. 6.15 DMA Controller
      1. 6.15.1 DMA Features
      2. 6.15.2 Default DMA Request Map
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
      4. 6.16.4 Network Time Synchronization Inputs
    17. 6.17 Error Signaling Module
      1. 6.17.1 ESM Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset/Abort/Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  I/O Timings
      1. 7.1.1 Input Timings
      2. 7.1.2 Output Timings
        1. 7.1.2.1 Low-EMI Output Buffers
    2. 7.2  Enhanced PWM Modules (ePWM)
      1. 7.2.1 ePWM Clocking and Reset
      2. 7.2.2 Synchronization of ePWMx Time-Base Counters
      3. 7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.2.5 ePWM Synchronization with External Devices
      6. 7.2.6 ePWM Trip Zones
        1. 7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.2.6.2 Trip Zone TZ4n
        3. 7.2.6.3 Trip Zone TZ5n
        4. 7.2.6.4 Trip Zone TZ6n
      7. 7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    3. 7.3  Enhanced Capture Modules (eCAP)
      1. 7.3.1 Clock Enable Control for eCAPx Modules
      2. 7.3.2 PWM Output Capability of eCAPx
      3. 7.3.3 Input Connection to eCAPx Modules
      4. 7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    4. 7.4  Enhanced Quadrature Encoder (eQEP)
      1. 7.4.1 Clock Enable Control for eQEPx Modules
      2. 7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.4.3 Input Connections to eQEPx Modules
      4. 7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    5. 7.5  12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.5.1 Features
      2. 7.5.2 Event Trigger Options
        1. 7.5.2.1 MibADC1 Event Trigger Hookup
        2. 7.5.2.2 MibADC2 Event Trigger Hookup
        3. 7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.5.3 ADC Electrical and Timing Specifications
      4. 7.5.4 Performance (Accuracy) Specifications
        1. 7.5.4.1 MibADC Nonlinearity Errors
        2. 7.5.4.2 MibADC Total Error
    6. 7.6  General-Purpose Input/Output
      1. 7.6.1 Features
    7. 7.7  Enhanced High-End Timer (N2HET)
      1. 7.7.1 Features
      2. 7.7.2 N2HET RAM Organization
      3. 7.7.3 Input Timing Specifications
      4. 7.7.4 N2HET1 to N2HET2 Synchronization
      5. 7.7.5 N2HET Checking
        1. 7.7.5.1 Internal Monitoring
        2. 7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.7.6 Disabling N2HET Outputs
      7. 7.7.7 High-End Timer Transfer Unit (HET)
        1. 7.7.7.1 Features
        2. 7.7.7.2 Trigger Connections
    8. 7.8  Controller Area Network (DCAN)
      1. 7.8.1 Features
      2. 7.8.2 Electrical and Timing Specifications
    9. 7.9  Local Interconnect Network Interface (LIN)
      1. 7.9.1 LIN Features
    10. 7.10 Serial Communication Interface (SCI)
      1. 7.10.1 Features
    11. 7.11 Inter-Integrated Circuit (I2C) Module
      1. 7.11.1 Features
      2. 7.11.2 I2C I/O Timing Specifications
    12. 7.12 Multibuffered / Standard Serial Peripheral Interface
      1. 7.12.1 Features
      2. 7.12.2 MibSPI Transmit and Receive RAM Organization
      3. 7.12.3 MibSPI Transmit Trigger Events
        1. 7.12.3.1 MibSPI1 Event Trigger Hookup
        2. 7.12.3.2 MibSPI3 Event Trigger Hookup
        3. 7.12.3.3 MibSPI5 Event Trigger Hookup
      4. 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.12.5 SPI Slave Mode I/O Timings
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Designs or Reference Designs
  9. 9 Device and Documentation Support
    1. 9.1  Getting Started and Next Steps
    2. 9.2  Device and Development-Support Tool Nomenclature
    3. 9.3  Tools and Software
      1. 9.3.1 Kits and Evaluation Modules for Hercules RM MCUs
      2. 9.3.2 Development Tools
      3. 9.3.3 Software
    4. 9.4  Documentation Support
    5. 9.5  Related Links
    6. 9.6  Community Resources
    7. 9.7  Trademarks
    8. 9.8  Electrostatic Discharge Caution
    9. 9.9  Glossary
    10. 9.10 Device Identification
      1. 9.10.1 Device Identification Code Register
      2. 9.10.2 Die Identification Registers
    11. 9.11 Module Certifications
      1. 9.11.1 DCAN Certification
      2. 9.11.2 LIN Certification
        1. 9.11.2.1 LIN Master Mode
        2. 9.11.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.11.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGE|144
  • PZ|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Device and Documentation Support

9.1 Getting Started and Next Steps

To get started using a RM Hercules™ ARM® Cortex®-R Microcontroller (MCU):

  1. Purchase a RM LaunchPad Development Kit with the LaunchPAD Quickstart Guide included.

    2. From the LaunchPAD Quickstart Guide, the user can easily determine the correct Code Composer Studio™ (CCS) Integrated Development Environment (IDE) and Hardware Abstraction Layer Code Generator (HALCoGen™) GUI-based chip configuration tool for any selected Hercules MCU device(s).

  2. Download the latest version of CCS IDE for Safety MCUs for the specified host platform (that is, Windows, Linux, or MacOS) (free as long as using a LaunchPAD or a Hercules MCU Development Kit [HDK])
  3. Under Order Now, download the HALCOGEN: HAL Code Generator tool.
  4. For additional tools and software descriptions, web page links, key docs, and so forth, see Tools and Software.

The Hercules RM family also has TI BoosterPack™ plug-in modules available that fit on top of a LaunchPad development kit.

9.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices.Each device has one of three prefixes: X, P, or null (no prefix) (for example, xRM44L920). These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices.

Device development evolutionary flow:

    x Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow.
    P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications.
    null Fully-qualified production device.

x and P devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

Figure 9-1 shows the numbering and symbol nomenclature for the RM44Lx20 devices.

RM44L920 RM44L520 device_numbering_conv_f5_spns229.gif Figure 9-1 RM44Lx20 Device Numbering Conventions

9.3 Tools and Software

TI offers an extensive line of tools and software for the Hercules™ Safety generation of MCUs including development tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

9.3.1 Kits and Evaluation Modules for Hercules RM MCUs

The RM Hercules™ ARM® Cortex®-R Microcontrollers (MCUs) offer a variety of hardware platforms to help speed development. From low-cost LaunchPad™ development kits to full-featured application developer platforms, the Hercules RM MCUs provide a wide range of hardware development tools designed to aid development and get customers to market faster.

Hercules™ RM46x LaunchPad™ Development Kit

LAUNCHXL2-RM46 — The Hercules RM46x LaunchPad development kit is a low-cost evaluation platform that helps users get started quickly in evaluating and developing with the Hercules microcontroller family, which is specifically designed for IEC 61508 functional safety applications. The LaunchPad features onboard emulation for programming and debugging; push-buttons; LEDs and ambient light sensor; and two standard 40-pin BoosterPack expansion connectors. Through the expansion connectors, the LaunchPad development kit can support a wide range of BoosterPack plug-in modules for added functionality (such as displays, wireless sensors, and so forth). LaunchPad development kits come preprogrammed with a demo code that lets the user easily learn the key safety, data acquisition, and control features of the Hercules MCU platform. For additional software downloads and other resources, visit the Hercules LaunchPads wiki.

9.3.2 Development Tools

Development tools includes both hardware and software development tools like integrated development environment (IDE), compilers, and emulators.

Software

Code Composer Studio™ (CCS) Integrated Development Environment (IDE) – Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.

CCS Uniflash Standalone Flash Tool for TI Microcontrollers (MCUs) [available free of charge] – CCS Uniflash is a standalone tool used to program the on-chip flash memory available on TI MCUs. The CCS Uniflash has a GUI, command line, and scripting interface.

SafeTI™ Compiler Qualification Kit – The SafeTI Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM or C2000 C/C++ Compiler to functional safety standards such as IEC 61508 SIL 3 and ISO 26262 ASIL D.

High-End Timer Integrated Development Environment (HET IDE) – The HET module available on the Hercules MCU devices is a programmable timer coprocessor that enables sophisticated functions for real-time control applications. The HET IDE is a windows-based application that provides an easy way to get started developing and debugging code for the HET module.

Hardware

Emulators

Below is a list of some emulators that can be used with the Hercules RM MCU devices. For a full list of emulators, click on the Emulators link above.

XDS100v2 – Low-cost, low-performance emulator – integrated on Hercules RM MCU Development Kits. With CCS IDE and IAR support.

XDS200 – The XDS200 is a JTAG emulator for TI embedded processors. Offering a balance of cost and performance, XDS200 emulator fits between the ultra-low cost XDS100 and the high-performance XDS560v2 products.

XDS560v2 – The XDS560™ family of emulators is designed to achieve high download speeds and is ideal for larger applications.

9.3.3 Software

Software includes Real-Time Operating Systems (RTOS), peripheral drivers, libraries, example code, and connectivity.

Hercules MCU software is designed to simplify and speed development of functional safety applications.

Hardware Abstraction Layer Code Generator (HALCoGen) for Hercules MCUs provides a graphical user interface that allows the user to configure peripherals, interrupts, clocks, and many other MCU parameters and can generate driver code which can be easily imported into integrated development environments like CCS IDE, IAR Workbench, etc. The HALCoGen tool also includes several example projects.

SafeTI HALCoGen Compliance Support Package (CSP) assists customers using HALCoGen to comply with functional safety standards by providing example documentation, reports, and unit-test capability.

The SafeTI Hercules Diagnostic Library is a software library of functions and response handlers for various safety features of the Hercules Safety MCUs.

SafeTI Hercules Diagnostic Library CSP assists customers using the SafeTI Diagnostic Library to comply with functional safety standards by providing documentation and reports.

Hercules™ Safety MCU Cortex®-R4 CMSIS DSP Library. The ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) includes over 60 functions covering vector operations, matrix computing, complex arithmetic, filter functions, control functions, PID controller, Fourier transforms, and many other frequently used DSP algorithms. Most algorithms are available in floating-point and various fixed-point formats and are optimized for the Cortex-R series processors.

Hercules™ F021 Flash API provides a software library of functions to program, erase, and verify F021 on-chip flash memory Hercules devices.

The Hercules™ RM MCUs are supported by many different Real-Time Operating Systems (RTOS) and Connectivity/Middleware options from various providers, some of which are safety certified.

9.4 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

The following documents describe the processor, related internal peripherals, and other technical collateral with respect to the RM44Lx microcontroller.

Errata

RM44Lx20 16/32-Bit RISC Flash Microcontroller Silicon Errata (Silicon Revision 0) (SPNZ209) describes the known exceptions to the functional specifications for the device.

RM44Lx20 16/32-Bit RISC Flash Microcontroller Silicon Errata (Silicon Revision A) (SPNZ231) describes the known exceptions to the functional specifications for the device.

Technical Reference Manuals

RM44Lx 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU608) details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.

Applications Reports

Compatibility Considerations: Migrating From RM48x or RM46x to RM44Lx20 Safety Microcontrollers (SPNA206) provides a summary of the differences between the RM44Lx20 versus the RM48x and RM46x series of microcontrollers.

9.5 Related Links

Table 9-1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY
RM44L920 Click here Click here Click here Click here Click here
RM44L520 Click here Click here Click here Click here Click here

9.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community The TI engineer-ro-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
    Hercules™ Safety Microcontrollers Forum TI's Hercules™ Safety Microcontrollers Forum was created under the E2E umbrella to foster collaboration among engineers, ask questions, share knowledge, explore ideas, and help solve problems, specifically relating to the Hercules Safety MCUs (that is, TMS570 and RM families).
    SafeTI™ Documentation Private E2E Forum A private E2E forum to request access to the safety analysis report; ask questions; share knowledge; and explore ideas to help resolve problems relating to the safety analysis report. This forum is closely monitored by the TI Safety experts. The safety analysis report itself includes detailed device-level Failure Modes, Effects, and Diagnostics Analysis (FMEDA) for ISO 26262 functional safety applications. The report also includes tools for estimating module and device-level failure rates (fault insertion tests (FIT) rates).

9.7 Trademarks

BoosterPack, Hercules, LaunchPad, XDS560, E2E are trademarks of Texas Instruments.

CoreSight is a registered trademark of ARM Limited (or its subsidiaries) in the EU and.

ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and.

All other trademarks are the property of their respective owners.

9.8 Electrostatic Discharge Caution

esds-image

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.9 Glossary

    TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9.10 Device Identification

9.10.1 Device Identification Code Register

The device identification code register at address 0xFFFFFFF0 identifies several aspects of the device including the silicon version. The details of the device identification code register are shown in Table 9-2. The device identification code register value for this device is:

  • Rev 0 = 0x8052AD05
  • Rev A = 0x8052AD0D

Figure 9-2 Device ID Bit Allocation Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP15 UNIQUE ID TECH
R-1 R-00000000101001 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TECH I/O VOLTAGE PERIPH PARITY FLASH ECC RAM ECC REVISION 1 0 1
R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-2 Device ID Bit Allocation Register Field Descriptions

BIT FIELD VALUE DESCRIPTION
31 CP15 Indicates the presence of coprocessor 15
1 CP15 present
30-17 UNIQUE ID 101001 Unique device identification number
This bitfield holds a unique number for a dedicated device configuration (die).
16-13 TECH Process technology on which the device is manufactured.
0101 F021
12 I/O VOLTAGE I/O voltage of the device.
0 I/O are 3.3 V
11 PERIPH PARITY 1 Peripheral Parity
Parity on peripheral memories
10-9 FLASH ECC Flash ECC
10 Program memory with ECC
8 RAM ECC Indicates if RAM ECC is present.
1 ECC implemented
7-3 REVISION Revision of the Device.
2-0 101 The platform family ID is always 0b101

9.10.2 Die Identification Registers

The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit dieid with the information as shown in Table 9-3.

Table 9-3 Die-ID Registers

ITEM NO. OF BITS BIT LOCATION
X Coord. on Wafer 12 0xFFFFFF7C[11:0]
Y Coord. on Wafer 12 0xFFFFFF7C[23:12]
Wafer # 8 0xFFFFFF7C[31:24]
Lot # 24 0xFFFFFF80[23:0]
Reserved 8 0xFFFFFF80[31:24]

9.11 Module Certifications

The following communications modules have received certification of adherence to a standard.

9.11.1 DCAN Certification

RM44L920 RM44L520 CAN_Certification_2011_02_08.png Figure 9-3 DCAN Certification

9.11.2 LIN Certification

9.11.2.1 LIN Master Mode

RM44L920 RM44L520 LIN_Certification_DLL21_Master_20121130_130513_TMS570LS_V1 0.png Figure 9-4 LIN Certification - Master Mode

9.11.2.2 LIN Slave Mode - Fixed Baud Rate

RM44L920 RM44L520 LIN_Certification_DLL21_Slave_Fixed_20121130_130513_TMS570LS_V1 0.png Figure 9-5 LIN Certification - Slave Mode - Fixed Baud Rate

9.11.2.3 LIN Slave Mode - Adaptive Baud Rate

RM44L920 RM44L520 new_LIN_Certification_Slave_Adapt.png Figure 9-6 LIN Certification - Slave Mode - Adaptive Baud Rate