SPNS229C October   2014  – November 2016 RM44L520 , RM44L920

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 PGE QFP Package Pinout (144-Pin)
      2. 4.1.2 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Signal Descriptions
      1. 4.2.1 PGE Package Terminal Functions
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.2.1.3  Enhanced Capture Modules (eCAP)
        4. 4.2.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.2.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.2.1.6  General-Purpose Input/Output (GIO)
        7. 4.2.1.7  Controller Area Network Controllers (DCAN)
        8. 4.2.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.2.1.9  Standard Serial Communication Interface (SCI)
        10. 4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.2.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.2.1.13 System Module Interface
        14. 4.2.1.14 Clock Inputs and Outputs
        15. 4.2.1.15 Test and Debug Modules Interface
        16. 4.2.1.16 Flash Supply and Test Pads
        17. 4.2.1.17 Supply for Core Logic: 1.2V nominal
        18. 4.2.1.18 Supply for I/O Cells: 3.3V nominal
        19. 4.2.1.19 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 PZ Package Terminal Functions
        1. 4.2.2.1  High-End Timer (N2HET) Modules
        2. 4.2.2.2  Enhanced Capture Modules (eCAP)
        3. 4.2.2.3  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        4. 4.2.2.4  Enhanced Pulse-Width Modulator Modules (ePWM)
        5. 4.2.2.5  General-Purpose Input/Output (GIO)
        6. 4.2.2.6  Controller Area Network Interface Modules (DCAN1, DCAN2)
        7. 4.2.2.7  Standard Serial Peripheral Interfaces (SPI2 and SPI4)
        8. 4.2.2.8  Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
        9. 4.2.2.9  Local Interconnect Network Controller (LIN)
        10. 4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
        11. 4.2.2.11 System Module Interface
        12. 4.2.2.12 Clock Inputs and Outputs
        13. 4.2.2.13 Test and Debug Modules Interface
        14. 4.2.2.14 Flash Supply and Test Pads
        15. 4.2.2.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.2.2.17 Ground Reference for All Supplies Except VCCAD
    3. 4.3 Pin Multiplexing
      1. 4.3.1 Output Multiplexing
      2. 4.3.2 Multiplexing of Inputs
    4. 4.4 Buffer Type
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions
    6. 5.6 Power Consumption Over Recommended Operating Conditions
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 SYSCLK (Frequencies)
        1. 5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains
        2. 5.8.1.2 Wait States Required - PGE and PZ Packages
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Module
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 Vectored Interrupt Manager
      1. 6.14.1 VIM Features
      2. 6.14.2 Interrupt Request Assignments
    15. 6.15 DMA Controller
      1. 6.15.1 DMA Features
      2. 6.15.2 Default DMA Request Map
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
      4. 6.16.4 Network Time Synchronization Inputs
    17. 6.17 Error Signaling Module
      1. 6.17.1 ESM Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset/Abort/Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  I/O Timings
      1. 7.1.1 Input Timings
      2. 7.1.2 Output Timings
        1. 7.1.2.1 Low-EMI Output Buffers
    2. 7.2  Enhanced PWM Modules (ePWM)
      1. 7.2.1 ePWM Clocking and Reset
      2. 7.2.2 Synchronization of ePWMx Time-Base Counters
      3. 7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.2.5 ePWM Synchronization with External Devices
      6. 7.2.6 ePWM Trip Zones
        1. 7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.2.6.2 Trip Zone TZ4n
        3. 7.2.6.3 Trip Zone TZ5n
        4. 7.2.6.4 Trip Zone TZ6n
      7. 7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    3. 7.3  Enhanced Capture Modules (eCAP)
      1. 7.3.1 Clock Enable Control for eCAPx Modules
      2. 7.3.2 PWM Output Capability of eCAPx
      3. 7.3.3 Input Connection to eCAPx Modules
      4. 7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    4. 7.4  Enhanced Quadrature Encoder (eQEP)
      1. 7.4.1 Clock Enable Control for eQEPx Modules
      2. 7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.4.3 Input Connections to eQEPx Modules
      4. 7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    5. 7.5  12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.5.1 Features
      2. 7.5.2 Event Trigger Options
        1. 7.5.2.1 MibADC1 Event Trigger Hookup
        2. 7.5.2.2 MibADC2 Event Trigger Hookup
        3. 7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.5.3 ADC Electrical and Timing Specifications
      4. 7.5.4 Performance (Accuracy) Specifications
        1. 7.5.4.1 MibADC Nonlinearity Errors
        2. 7.5.4.2 MibADC Total Error
    6. 7.6  General-Purpose Input/Output
      1. 7.6.1 Features
    7. 7.7  Enhanced High-End Timer (N2HET)
      1. 7.7.1 Features
      2. 7.7.2 N2HET RAM Organization
      3. 7.7.3 Input Timing Specifications
      4. 7.7.4 N2HET1 to N2HET2 Synchronization
      5. 7.7.5 N2HET Checking
        1. 7.7.5.1 Internal Monitoring
        2. 7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.7.6 Disabling N2HET Outputs
      7. 7.7.7 High-End Timer Transfer Unit (HET)
        1. 7.7.7.1 Features
        2. 7.7.7.2 Trigger Connections
    8. 7.8  Controller Area Network (DCAN)
      1. 7.8.1 Features
      2. 7.8.2 Electrical and Timing Specifications
    9. 7.9  Local Interconnect Network Interface (LIN)
      1. 7.9.1 LIN Features
    10. 7.10 Serial Communication Interface (SCI)
      1. 7.10.1 Features
    11. 7.11 Inter-Integrated Circuit (I2C) Module
      1. 7.11.1 Features
      2. 7.11.2 I2C I/O Timing Specifications
    12. 7.12 Multibuffered / Standard Serial Peripheral Interface
      1. 7.12.1 Features
      2. 7.12.2 MibSPI Transmit and Receive RAM Organization
      3. 7.12.3 MibSPI Transmit Trigger Events
        1. 7.12.3.1 MibSPI1 Event Trigger Hookup
        2. 7.12.3.2 MibSPI3 Event Trigger Hookup
        3. 7.12.3.3 MibSPI5 Event Trigger Hookup
      4. 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.12.5 SPI Slave Mode I/O Timings
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Designs or Reference Designs
  9. 9 Device and Documentation Support
    1. 9.1  Getting Started and Next Steps
    2. 9.2  Device and Development-Support Tool Nomenclature
    3. 9.3  Tools and Software
      1. 9.3.1 Kits and Evaluation Modules for Hercules RM MCUs
      2. 9.3.2 Development Tools
      3. 9.3.3 Software
    4. 9.4  Documentation Support
    5. 9.5  Related Links
    6. 9.6  Community Resources
    7. 9.7  Trademarks
    8. 9.8  Electrostatic Discharge Caution
    9. 9.9  Glossary
    10. 9.10 Device Identification
      1. 9.10.1 Device Identification Code Register
      2. 9.10.2 Die Identification Registers
    11. 9.11 Module Certifications
      1. 9.11.1 DCAN Certification
      2. 9.11.2 LIN Certification
        1. 9.11.2.1 LIN Master Mode
        2. 9.11.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.11.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGE|144
  • PZ|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

Over Operating Free-Air Temperature Range
MIN MAX UNIT
Supply voltage range: VCC(2) –0.3 1.43 V
VCCIO, VCCP(2) –0.3 4.6
VCCAD(2) –0.3 6.25
Input voltage All input pins, with exception of ADC pins –0.3 4.6 V
ADC input pins –0.3 6.25
Output voltage All output pins –0.3 4.6 V
Input clamp current IIK (VI < 0 or VI > VCCIO)
All pins, except AD1IN[23:0] or AD2IN[15:0]		 –20 20 mA
IIK (VI < 0 or VI > VCCAD)
AD1IN[23:0] or AD2IN[15:0]		 –10 10
Total –40 40
Output clamp current IOK (VO < 0 or VO > VCCIO)
All pins, except AWM1_EXT_x		 –20 20 mA
Total –40 40
Operating free-air temperature (TA) –40 105 °C
Operating junction temperature (TJ) –40 130 °C
Storage temperature (Tstg) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge (ESD) performance: Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2 kV
Charged Device Model (CDM), per JESD22-C101(2) All pins ±250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On Hours (POH)(1)(2)

NOMINAL CVDD VOLTAGE (V) JUNCTION
TEMPERATURE (Tj) 		LIFETIME POH
1.2 105ºC 100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207).

5.4 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS MIN NOM MAX UNIT
VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V
VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V
VCCAD MibADC supply voltage 3 5.25 V
VCCP Flash pump supply voltage 3 3.3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD MibADC supply ground –0.1 0.1 V
VADREFHI Analog-to-digital high-voltage reference source VSSAD VCCAD V
VADREFLO Analog-to-digital low-voltage reference source VSSAD VCCAD V
VSLEW Maximum positive slew rate for VCCIO, VCCAD and VCPP supplies 1 V/μs
Vhys Input hysteresis All inputs 180 mV
VIL Low-level input voltage All inputs –0.3 0.8 V
VIH High-level input voltage All inputs 2 VCCIO + 0.3 V
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature(2) –40 130 °C
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage IOL = IOLmax 0.2VCCIO V
IOL = 50 µA, standard output mode 0.2
IOL = 50 µA, low-EMI output mode
(see Section 7.1.2.1)		 0.2VCCIO
VOH High-level output voltage IOH = IOHmax 0.8VCCIO V
IOH = 50 µA, standard output mode VCCIO - 0.3
IOH = 50 µA, low-EMI output mode
(see Section 7.1.2.1)		 0.8VCCIO
IIC Input clamp current (I/O pins) VI < VSSIO - 0.3 or
VI > VCCIO + 0.3		 –3.5 3.5 mA
II Input current (I/O pins) IIH Pulldown 20 µA VI = VCCIO 5 40 µA
IIH Pulldown 100 µA VI = VCCIO 40 195
IIL Pullup 20 µA VI = VSS –40 –5
IIL Pullup 100 µA VI = VSS –195 –40
All other pins No pullup or pulldown –1 1
CI Input capacitance 2 pF
CO Output capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

5.6 Power Consumption Over Recommended Operating Conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC VCC digital supply current (operating mode)
fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax		 fHCLK = 120 MHz 120(3) 260(1) mA
fHCLK = 180 MHz 170(3) 310(1)
VCC digital supply current (LBIST/PBIST mode) LBIST/PBIST clock frequency = 100 MHz 290 (3) 460(2)(4) mA
ICCIO VCCIO digital supply current (operating mode) No DC load, VCCmax 15 mA
ICCAD VCCAD supply current (operating mode) Single ADC operational, VCCADmax 15 mA
Both ADCs operational, VCCADmax 30
ICCREFHI ADREFHI supply current (operating mode) Single ADC operational, ADREFHImax 3 mA
Both ADCs operational, ADREFHImax 6
ICCP VCCP supply current Read from 1 bank and program another bank, VCCPmax 55 mA
(1) The maximum ICC, value can be derated
  • linearly with voltage
  • by 0.85 mA/MHz for lower operating frequency when fHCLK= 2 * fVCLK
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    88 - 0.005 e0.024 TJK
(2) The maximum ICC, value can be derated
  • linearly with voltage
  • by 0.85 mA/MHz for lower operating frequency
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    88 - 0.005 e0.024 TJK
(3) The typical value is the average current for the nominal process corner and junction temperature of 25°C.
(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the device and the voltage regulator.

5.7 Thermal Resistance Characteristics

Table 5-1 shows the thermal resistance characteristics for the QFP - PGE mechanical package.

Table 5-2 shows the thermal resistance characteristics for the QFP - PZ mechanical package.

Table 5-1 Thermal Resistance Characteristics (PGE Package)

°C/W
RΘJA Junction-to-free air thermal resistance, still air using JEDEC 2S2P test board 37.5
RΘJB Junction-to-board thermal resistance 19.7
RΘJC Junction-to-case thermal resistance 9.4
ΨJT Junction-to-package top, Still air 0.40

Table 5-2 Thermal Resistance Characteristics (PZ Package)

°C/W
RΘJA Junction-to-free air thermal resistance, still air using JEDEC 2S2P test board 43.5
RΘJB Junction-to-board thermal resistance 21.6
RΘJC Junction-to-case thermal resistance 11.2
ΨJT Junction-to-package top, Still air 0.50

5.8 Timing and Switching Characteristics

5.8.1 SYSCLK (Frequencies)

5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains

Table 5-3 Clock Domain Timing Specifications

PARAMETER DESCRIPTION CONDITIONS MIN MAX UNIT
fGCLK GCLK - CPU clock frequency fHCLK MHz
fVCLK4 VCLK4 - Secondary peripheral clock frequency 150 MHz
fHCLK HCLK - System clock frequency PZ Pipeline mode enabled 120 MHz
Pipeline mode disabled 50 MHz
PGE Pipeline mode enabled 180 MHz
Pipeline mode disabled 50 MHz
fVCLK VCLK - Primary peripheral clock frequency 100 MHz
fVCLK2 VCLK2 - Secondary peripheral clock frequency 100 MHz
fVCLKA1 VCLKA1 - Primary asynchronous peripheral clock frequency 100 MHz
fRTICLK RTICLK - Clock frequency fVCLK MHz

5.8.1.2 Wait States Required - PGE and PZ Packages

RM44L920 RM44L520 wait_states_new_spns225_180MHz.gif Figure 5-1 Wait States Scheme — PGE, 180 MHz
RM44L920 RM44L520 wait_states_new_spns229_120MHz.gif Figure 5-2 Wait States Scheme — PZ, 120 MHz

As shown in Figure 5-1 and Figure 5-2, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.

The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 180 MHz in pipelined mode for the PGE Package, and 120  MHz for the PZ package.

The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state.