SPNS183C September   2012  – June 2015 RM46L440 , RM46L840

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.1.3  Enhanced Capture Modules (eCAP)
        4. 4.3.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.1.6  General-Purpose Input / Output (GPIO)
        7. 4.3.1.7  Controller Area Network Controllers (DCAN)
        8. 4.3.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.1.9  Standard Serial Communication Interface (SCI)
        10. 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.1.13 Ethernet Controller
        14. 4.3.1.14 System Module Interface
        15. 4.3.1.15 Clock Inputs and Outputs
        16. 4.3.1.16 Test and Debug Modules Interface
        17. 4.3.1.17 Flash Supply and Test Pads
        18. 4.3.1.18 Supply for Core Logic: 1.2V nominal
        19. 4.3.1.19 Supply for I/O Cells: 3.3V nominal
        20. 4.3.1.20 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.2.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.2.3  Enhanced Capture Modules (eCAP)
        4. 4.3.2.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.2.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.2.6  General-Purpose Input / Output (GPIO)
        7. 4.3.2.7  Controller Area Network Controllers (DCAN)
        8. 4.3.2.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.2.9  Standard Serial Communication Interface (SCI)
        10. 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.2.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.2.13 Ethernet Controller
        14. 4.3.2.14 External Memory Interface (EMIF)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2V nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3V nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption Over Recommended Operating Conditions
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate clock tree after GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
        3. 6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
      6. 6.9.6 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1 Block Diagram
      2. 6.21.2 Debug Components Memory Map
      3. 6.21.3 JTAG Identification Code
      4. 6.21.4 Debug ROM
      5. 6.21.5 JTAG Scan Interface Timings
      6. 6.21.6 Advanced JTAG Security Module
      7. 6.21.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Timings
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connections to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  Multibuffered 12bit Analog-to-Digital Converter
      1. 7.4.1 Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MIBADC1 Event Trigger Hookup
        2. 7.4.2.2 MIBADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Synchronization
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HTU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.12.3 Management Data Input/Output (MDIO)
  8. 8Device and Documentation Support
    1. 8.1 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Related Links
      3. 8.2.3 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 DCAN Certification
      2. 8.7.2 LIN Certification
        1. 8.7.2.1 LIN Master Mode
        2. 8.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PGE|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (1)

MIN MAX UNIT
Supply voltage range: VCC(2) -0.3 1.43 V
VCCIO, VCCP(2) -0.3 4.6 V
VCCAD -0.3 6.25 V
Input voltage range: All input pins, with exception of ADC pins -0.3 4.6 V
ADC input pins -0.3 6.25 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins, except AD1IN[23:0] or AD2IN[15:0]		 -20 +20 mA
IIK (VI < 0 or VI > VCCAD)
AD1IN[23:0] or AD2IN[15:0]		 -10 +10 mA
Total -40 +40 mA
Operating free-air temperature range, TA: -40 105 °C
Operating junction temperature range, TJ: -40 130 °C
Storage temperature range, Tstg -65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds.

5.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge (ESD) performance: Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2 kV
Charged device model (CDM), per JESD22-C101(2) All pins ±250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On Hours (POH)(1)(2)

NOMINAL CORE VOLTAGE (VCC) JUNCTION
TEMPERATURE (Tj) 		LIFETIME POH
1.2 105ºC 100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207).

5.4 Device Recommended Operating Conditions(1)

MIN NOM MAX UNIT
VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V
VCCPLL PLL Supply Voltage 1.14 1.2 1.32 V
VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V
VCCAD MibADC supply voltage 3 5.25 V
VCCP Flash pump supply voltage 3 3.3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD MibADC supply ground -0.1 0.1 V
VADREFHI A-to-D high-voltage reference source VSSAD VCCAD V
VADREFLO A-to-D low-voltage reference source VSSAD VCCAD V
VSLEW Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies 1 V/µs
TA Operating free-air temperature -40 105 °C
TJ Operating junction temperature(2) -40 130 °C
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains

Table 5-1 Clock Domain Timing Specifications

PARAMETER DESCRIPTION CONDITIONS MAX UNIT
fHCLK HCLK - System clock frequency Pipeline mode enabled 200 MHz
Pipeline mode disabled 50 MHz
fGCLK GCLK - CPU clock frequency fHCLK MHz
fVCLK VCLK - Primary peripheral clock frequency 100 MHz
fVCLK2 VCLK2 - Secondary peripheral clock frequency 100 MHz
fVCLK3 VCLK3 - Secondary peripheral clock frequency 100 MHz
fVCLK4 VCLK4 - Secondary peripheral clock frequency 150 MHz
fVCLKA1 VCLKA1 - Primary asynchronous peripheral clock frequency 100 MHz
fVCLKA2 VCLKA2 - Secondary asynchronous peripheral clock frequency 100 MHz
fVCLKA3 VCLKA3 - Primary asynchronous peripheral clock frequency 100 MHz
fVCLKA4 VCLKA4 - Secondary asynchronous peripheral clock frequency 100 MHz
fRTICLK RTICLK - clock frequency fVCLK MHz

5.6 Wait States Required

RM46L440 RM46L840 wait_states_150mhz_pns185.gifFigure 5-1 Wait States Scheme

As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.

The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 200 MHz in pipelined mode with one address wait state and three data wait states.

The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state.

5.7 Power Consumption Over Recommended Operating Conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC VCC digital supply current (operating mode)
fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax		 fHCLK = 200MHz 205(3) 340(1) mA
VCC Digital supply current (LBIST/PBIST mode)

LBIST/PBIST clock frequency = 100MHz

 265(3) 455(2)(4) mA
ICCPLL VCCPLL digital supply current (operating mode) VCCPLL = VCCPLLmax 10 mA
ICCIO VCCIO Digital supply current (operating mode. No DC load, VCCmax 10 mA
ICCAD VCCAD supply current (operating mode) Single ADC operational, VCCADmax 15 mA
Both ADCs operational, VCCADmax 30
IADREFHI ADREFHI supply current (operating mode) Single ADC operational, ADREFHImax 3 mA
Both ADCs operational, ADREFHImax 6
ICCP VCCP supply current read from 1 bank and program another bank, VCCPmax 55 mA
(1) The maximum ICC, value can be derated
  • linearly with voltage
  • by 1 ma/MHz for lower operating frequency when fHCLK= 2 * fVCLK
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    120 - 0.068 e0.0185 TJK
(2) The maximum ICC, value can be derated
  • linearly with voltage
  • by 1.5 ma/MHz for lower operating frequency
  • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.

    120 - 0.068 e0.0185 TJK
(3) The typical value is the average current for the nominal process corner and junction temperature of 25C.
(4) LBIST and PBIST currents are for a short duration, typically less than 10ms. They are usually ignored for thermal calculations for the device and the voltage regulator

5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vhys Input hysteresis All inputs 180 mV
VIL Low-level input voltage All inputs -0.3 0.8 V
VIH High-level input voltage All inputs 2 VCCIO + 0.3 V
VOL Low-level output voltage IOL = IOLmax 0.2 VCCIO V
IOL = 50 µA, standard output mode 0.2
IOL = 50 µA, low-EMI output mode (see Section 5.13) 0.2 VCCIO
VOH High-level output voltage IOH = IOHmax 0.8 VCCIO V
IOH = 50 µA, standard output mode VCCIO -0.3
IOH = 50 µA, low-EMI output mode (see Section 5.13) 0.8 VCCIO
IIK Input clamp current (I/O pins)(2) VI < VSSIO - 0.3 or VI > VCCIO + 0.3 -3.5 3.5 mA
II Input current (I/O pins) IIH Pulldown 20µA VI = VCCIO 5 40 µA
IIH Pulldown 100µA VI = VCCIO 40 195
IIL Pullup 20µA VI = VSS -40 -5
IIL Pullup 100µA VI = VSS -195 -40
All other pins No pullup or pulldown -1 1
CI Input capacitance 2 pF
CO Output capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) If the input voltage extends outside of the range VIL to VIH then the input current must be limited to IIK to maintain proper operation. See the application note SPNA201 for more information on limiting input clamp currents.

5.9 Thermal Resistance Characteristics

Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.

Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.

Table 5-2 Thermal Resistance Characteristics (PGE Package)

°C/W
RΘJA Junction-to-free air thermal resistance, Still air using JEDEC 2S2P test board 40
RΘJB Junction-to-board thermal resistance 27.2
RΘJC Junction-to-case thermal resistance 7.3
ΨJT Junction-to-package top, Still air 0.10

Table 5-3 Thermal Resistance Characteristics (ZWT Package)

°C/W
RΘJA Junction-to-free air thermal resistance, Still air (includes 5x5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 18.8
RΘJB Junction-to-board thermal resistance 14.1
RΘJC Junction-to-case thermal resistance 7.1
ΨJT Junction-to-package top, Still air (includes 5x5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 0.33

5.10 Output Buffer Drive Strengths

Table 5-4 Output Buffer Drive Strengths

LOW-LEVEL OUTPUT CURRENT,
IOL for VI=VOLmax
or
HIGH-LEVEL OUTPUT CURRENT,
IOH for VI=VOHmin		 SIGNALS
8 mA

MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],

TMS, TDI, TDO, RTCK,

SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR,

N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15]

ECAP1, ECAP4, ECAP5, ECAP6

EQEP1I, EQEP1S, EQEP2I, EQEP2S

EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B

EMIF_ADDR[0:12], EMIF_BA[0:1], EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15], EMIF_nCAS, EMIF_nCS[0:4], EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE, EMIF_RNW

MDCLK, MDIO, MII_RX_VCLKA4, MII_TX_VCLKA4, MII_TXD[0:3], MII_TXEN, RMII_REFCLK, RMII_TXD[0:1], RMII_TXEN
4 mA

TEST,

MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,

ECAP2, ECAP3

nRST
2 mA zero-dominant

AD1EVT,

CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,

GIOA[0-7], GIOB[0-7],

LINRX, LINTX,

MIBSPI1nCS[0], MIBSPI1nCS[1-3], MIBSPI1nENA, MIBSPI3nCS[0-3], MIBSPI3nENA, MIBSPI5nCS[0-3], MIBSPI5nENA,

N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15], N2HET2[16], N2HET2[18],

SPI2nCS[0], SPI2nENA, SPI4nCS[0], SPI4nENA

selectable 8 mA / 2 mA

ECLK,

SPI2CLK, SPI2SIMO, SPI2SOMI

The default output buffer drive strength is 8 mA for these signals.

Table 5-5 Selectable 8 mA/2 mA Control

Signal Control Bit Address 8 mA 2 mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11](1) 0xFFF7 F668 0 1
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits differ, SPI2PC9[11] determines the drive strength.

5.11 Input Timings

RM46L440 RM46L840 ttl_inputs_pns160.gifFigure 5-2 TTL-Level Inputs

Table 5-6 Timing Requirements for Inputs(1)

Parameter MIN MAX Unit
tpw Input minimum pulse width tc(VCLK) + 10(2) ns
tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL 1 ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown above is only valid for pin used in general-purpose input mode.

5.12 Output Timings

Table 5-7 Switching Characteristics for Output Timings versus Load Capacitance ©L)

Parameter MIN MAX Unit
Rise time, tr 8 mA low EMI pins
(see Table 5-4)		 CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 4 mA low EMI pins
(see Table 5-4)		 CL = 15 pF 5.6 ns
CL = 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Fall time, tf CL = 15 pF 5.6 ns
CL= 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Rise time, tr 2 mA-z low EMI pins
(see Table 5-4)		 CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Rise time, tr Selectable 8 mA / 2 mA-z pins
(see Table 5-4)		 8 mA mode CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 2 mA-z mode CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
RM46L440 RM46L840 cmos_outputs_pns160.gifFigure 5-3 CMOS-Level Outputs

Table 5-8 Timing Requirements for Outputs(1)

Parameter MIN MAX UNIT
td(parallel_out) Delay between low to high, or high to low transition of general-purpose output signals that can be configured by an application in parallel, e.g. all signals in a GIOA port, or all N2HET1 signals, etc. 6 ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 5-4 for output buffer drive strength information on each signal.

5.13 Low-EMI Output Buffers

The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads.

This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively.

Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW.

Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so as to maintain the output voltage at or above VREFHIGH.

The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.

Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an issue since the actual clamp current capability is always greater than the IOH / IOL specifications.

The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode.

Table 5-9 Low-EMI Output Buffer Hookup

Module or Signal Name Control Register to Enable Low-EMI Mode
Module: MibSPI1 GPREG1.0
Module: SPI2 GPREG1.1
Module: MibSPI3 GPREG1.2
Reserved GPREG1.3
Module: MibSPI5 GPREG1.4
Reserved GPREG1.5
Module: EMIF GPREG1.6
Reserved GPREG1.7
Signal: TMS GPREG1.8
Signal: TDI GPREG1.9
Signal: TDO GPREG1.10
Signal: RTCK GPREG1.11
Signal: TEST GPREG1.12
Signal: nERROR GPREG1.13
Signal: AD1EVT GPREG1.14