SPNS183C September   2012  – June 2015 RM46L440 , RM46L840

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.1.3  Enhanced Capture Modules (eCAP)
        4. 4.3.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.1.6  General-Purpose Input / Output (GPIO)
        7. 4.3.1.7  Controller Area Network Controllers (DCAN)
        8. 4.3.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.1.9  Standard Serial Communication Interface (SCI)
        10. 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.1.13 Ethernet Controller
        14. 4.3.1.14 System Module Interface
        15. 4.3.1.15 Clock Inputs and Outputs
        16. 4.3.1.16 Test and Debug Modules Interface
        17. 4.3.1.17 Flash Supply and Test Pads
        18. 4.3.1.18 Supply for Core Logic: 1.2V nominal
        19. 4.3.1.19 Supply for I/O Cells: 3.3V nominal
        20. 4.3.1.20 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.2.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.2.3  Enhanced Capture Modules (eCAP)
        4. 4.3.2.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.2.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.2.6  General-Purpose Input / Output (GPIO)
        7. 4.3.2.7  Controller Area Network Controllers (DCAN)
        8. 4.3.2.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.2.9  Standard Serial Communication Interface (SCI)
        10. 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.2.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.2.13 Ethernet Controller
        14. 4.3.2.14 External Memory Interface (EMIF)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2V nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3V nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption Over Recommended Operating Conditions
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate clock tree after GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
        3. 6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
      6. 6.9.6 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1 Block Diagram
      2. 6.21.2 Debug Components Memory Map
      3. 6.21.3 JTAG Identification Code
      4. 6.21.4 Debug ROM
      5. 6.21.5 JTAG Scan Interface Timings
      6. 6.21.6 Advanced JTAG Security Module
      7. 6.21.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Timings
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connections to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  Multibuffered 12bit Analog-to-Digital Converter
      1. 7.4.1 Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MIBADC1 Event Trigger Hookup
        2. 7.4.2.2 MIBADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Synchronization
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HTU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.12.3 Management Data Input/Output (MDIO)
  8. 8Device and Documentation Support
    1. 8.1 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Related Links
      3. 8.2.3 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 DCAN Certification
      2. 8.7.2 LIN Certification
        1. 8.7.2.1 LIN Master Mode
        2. 8.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PGE|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 PGE QFP Package Pinout (144-Pin)

RM46L440 RM46L840 PGE_144A_spns185.gifFigure 4-1 PGE QFP Package Pinout (144-Pin)

Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.

4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)

RM46L440 RM46L840 337ZWT_non_automotive_ball_map.gifFigure 4-2 ZWT Package Pinout. Top View

Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.

4.3 Terminal Functions

Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a functional pin/ball description. The first signal name listed is the primary function for that terminal. The signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) chapter of the RM46x Technical Reference Manual (SPNU514).

NOTE

In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.


All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.


All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.

4.3.1 PGE Package

4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)

Table 4-1 PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
ADREFHI(1) 66 Power N/A None ADC high reference supply
ADREFLO(1) 67 Power ADC low reference supply
VCCAD(1) 69 Power Operating supply for ADC
VSSAD(1) 68 Ground
AD1EVT/MII_RX_ER/RMII_RX_ER 86 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 55 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO
AD1IN[0] 60 Input N/A None ADC1 analog input
AD1IN[1] 71
AD1IN[2] 73
AD1IN[3] 74
AD1IN[4] 76
AD1IN[5] 78
AD1IN[6] 80
AD1IN[7] 61
AD1IN[8] / AD2IN[8] 83 Input N/A None ADC1/ADC2 shared analog inputs
AD1IN[9] / AD2IN[9] 70
AD1IN[10] / AD2IN[10] 72
AD1IN[11] / AD2IN[11] 75
AD1IN[12] / AD2IN[12] 77
AD1IN[13] / AD2IN[13] 79
AD1IN[14] / AD2IN[14] 82
AD1IN[15] / AD2IN[15] 85
AD1IN[16] / AD2IN[0] 58
AD1IN[17] / AD2IN[1] 59
AD1IN[18] / AD2IN[2] 62
AD1IN[19] / AD2IN[3] 63
AD1IN[20] / AD2IN[4] 64
AD1IN[21] / AD2IN[5] 65
AD1IN[22] / AD2IN[6] 81
AD1IN[23] / AD2IN[7] 84
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 Output Pullup None AWM1 external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Output Pullup None AWM1 external analog mux select line0
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Output Pullup None AWM1 external analog mux select line0
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

4.3.1.2 Enhanced High-End Timer Modules (N2HET)

Table 4-2 PGE Enhanced High-End Timer Modules (N2HET)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[0]/SPI4CLK/EPWM2B 25 I/O Pulldown Programmable, 20 µA

N2HET1 time input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23
N2HET1[2]/SPI4SIMO[0]/EPWM3A 30
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24
N2HET1[4]/EPWM4B 36
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31
N2HET1[6]/SCIRX/EPWM5A 38
N2HET1[7]/N2HET2[14]/EPWM7B 33
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106
N2HET1[9]/N2HET2[16]/EPWM7A 35
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ EPWM1SYNCO 6
N2HET1[12]/MII_CRS/RMII_CRS_DV 124
N2HET1[13]/SCITX/EPWM5B 39
N2HET1[14] 125
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/EQEP1S 130 Pullup
N2HET1[18]/EPWM6A 140 Pulldown
MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 Pullup
N2HET1[20]/EPWM6B 141 Pulldown
N2HET1[22] 15
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 96 Pullup
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 Pulldown
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pullup
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 Pulldown
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 Pullup
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 107 Pulldown
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 Pullup
N2HET1[30]/MII_RX_DV/EQEP2S 127 Pulldown
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pullup
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 I/O Pulldown Programmable, 20 µA(1) Disable selected PWM outputs
GIOA[2]/N2HET2[0]/ EQEP2I 9 I/O Pulldown Programmable, 20 µA

N2HET2 time input capture or output compare, or GPIO

Each terminal has a suppression filter with a programmable duration.
GIOA[6]/N2HET2[4]/EPWM1B 16
GIOA[7]/N2HET2[6]/EPWM2A 22
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31
N2HET1[7]/N2HET2[14]/EPWM7B 33
N2HET1[9]/N2HET2[16]/EPWM7A 35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ EPWM1SYNCO 6
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 55 I/O Pullup Programmable, 20 µA(1) Disable selected PWM outputs
(1) The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is controlled by the function which is selected by the output mux control for this terminal.

4.3.1.3 Enhanced Capture Modules (eCAP)

Table 4-3 PGE Enhanced Capture Modules (eCAP)(1)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 I/O Pulldown Fixed 20 µA
Pullup		 Enhanced Capture Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 Pullup Enhanced Capture Module 2 I/O
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Enhanced Capture Module 3 I/O
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 96 Enhanced Capture Module 4 I/O
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ ECAP5 97 Enhanced Capture Module 5 I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 105 Enhanced Capture Module 6 I/O
(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-4 PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Input Pullup Fixed 20 µA
Pullup		 Enhanced QEP1 Input A
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Input Enhanced QEP1 Input B
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 55 I/O Enhanced QEP1 Index
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/EQEP1S 130 I/O Enhanced QEP1 Strobe
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23 Input Pulldown Enhanced QEP2 Input A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 Input Enhanced QEP2 Input B
GIOA[2]/N2HET2[0]/ EQEP2I 9 I/O Enhanced QEP2 Index
N2HET1[30]/MII_RX_DV/EQEP2S 127 I/O Enhanced QEP2 Strobe
(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-5 PGE Enhanced Pulse-Width Modulator Modules (ePWM)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 Output Pulldown None Enhanced PWM1 Output A
GIOA[6]/N2HET2[4]/EPWM1B 16 Enhanced PWM1 Output B
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 External ePWM Sync Pulse Output
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139 Input Fixed 20 µA
Pullup		 External ePWM Sync Pulse Input
GIOA[7]/N2HET2[6]/EPWM2A 22 Output None Enhanced PWM2 Output A
N2HET1[0]/SPI4CLK/EPWM2B 25 Enhanced PWM2 Output B
N2HET1[2]/SPI4SIMO[0]/EPWM3A 30 Enhanced PWM3 Output A
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 Enhanced PWM3 Output B
MIBSPI5NCS[0]/EPWM4A 32 Pullup Enhanced PWM4 Output A
N2HET1[4]/EPWM4B 36 Pulldown Enhanced PWM4 Output B
N2HET1[6]/SCIRX/EPWM5A 38 Enhanced PWM5 Output A
N2HET1[13]/SCITX/EPWM5B 39 Enhanced PWM5 Output B
N2HET1[18]/EPWM6A 140 Enhanced PWM6 Output A
N2HET1[20]/EPWM6B 141 Enhanced PWM6 Output B
N2HET1[9]/N2HET2[16]/EPWM7A 35 Enhanced PWM7 Output A
N2HET1[7]/N2HET2[14]/EPWM7B 33 Enhanced PWM7 Output B
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 Input Pullup Fixed 20 µA
Pullup		 Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs.
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 118 Pulldown

4.3.1.6 General-Purpose Input / Output (GPIO)

Table 4-6 PGE General-Purpose Input / Output (GPIO)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
GIOA[0] 2 I/O Pulldown Programmable, 20 µA General-purpose I/O.
All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges.
GIOA[1] 5
GIOA[2]/N2HET2[0] /EQEP2I 9
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14
GIOA[6]/N2HET2[4]/EPWM1B 16
GIOA[7]/N2HET2[6]/EPWM2A 22
GIOB[0] 126
GIOB[1] 133
GIOB[2] 142
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 55(1) Pullup
GIOB[3] 1 Pulldown
(1) GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pullup is enabled on the input. This is not programmable using the GIO module control registers.

4.3.1.7 Controller Area Network Controllers (DCAN)

Table 4-7 PGE Controller Area Network Controllers (DCAN)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
CAN1RX 90 I/O Pullup Programmable, 20 µA CAN1 receive, or GPIO
CAN1TX 89 CAN1 transmit, or GPIO
CAN2RX 129 CAN2 receive, or GPIO
CAN2TX 128 CAN2 transmit, or GPIO
CAN3RX 12 CAN3 receive, or GPIO
CAN3TX 13 CAN3 transmit, or GPIO

4.3.1.8 Local Interconnect Network Interface Module (LIN)

Table 4-8 PGE Local Interconnect Network Interface Module (LIN)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
LINRX 131 I/O Pullup Programmable, 20 µA LIN receive, or GPIO
LINTX 132 LIN transmit, or GPIO

4.3.1.9 Standard Serial Communication Interface (SCI)

Table 4-9 PGE Standard Serial Communication Interface (SCI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[6]/SCIRX/EPWM5A 38 I/O Pulldown Programmable, 20 µA SCI receive, or GPIO
N2HET1[13]/SCITX/EPWM5B 39 SCI transmit, or GPIO

4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)

Table 4-10 PGE Inter-Integrated Circuit Interface Module (I2C)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 I/O Pullup Programmable, 20 µA I2C serial data, or GPIO
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 I2C serial clock, or GPIO

4.3.1.11 Standard Serial Peripheral Interface (SPI)

Table 4-11 PGE Standard Serial Peripheral Interface (SPI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[0]/SPI4CLK/EPWM2B 25 I/O Pulldown Programmable, 20 µA SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23 SPI4 enable, or GPIO
N2HET1[2]/SPI4SIMO[0]/EPWM3A 30 SPI4 slave-input master-output, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 SPI4 slave-output master-input, or GPIO

4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-12 PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI1CLK 95 I/O Pullup Programmable, 20 µA MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 105 MibSPI1 chip select, or GPIO
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/EQEP1S 130
MIBSPI1NCS[2]/N2HET1[19]/MDIO 40
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 Pulldown Programmable, 20 µA MibSPI1 chip select, or GPIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 96 Pullup Programmable, 20 µA MibSPI1 enable, or GPIO
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown Programmable, 20 µA MibSPI1 slave-in master-out, or GPIO
MIBSPI1SOMI[0] 94 Pullup Programmable, 20 µA MibSPI1 slave-out master-in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 105
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 I/O Pullup Programmable, 20 µA MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 55 MibSPI3 chip select, or GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 Pulldown Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pullup Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-in master-out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-out master-in, or GPIO
MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 I/O Pullup Programmable, 20 µA MibSPI5 clock, or GPIO
MIBSPI5NCS[0]/EPWM4A 32 MibSPI5 chip select, or GPIO
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ ECAP5 97 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MibSPI5 slave-in master-out, or GPIO
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MibSPI5 slave-out master-in, or GPIO
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ ECAP5 97 MibSPI5 slave-out master-in, or GPIO
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MibSPI5 slave-out master-in, or GPIO

4.3.1.13 Ethernet Controller

Table 4-13 PGE Ethernet Controller: MDIO Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output Pullup None Serial clock output
MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pullup Fixed 20 µA
Pullup		 Serial data input/output

Table 4-14 PGE Ethernet Controller: Reduced Media Independent Interface (RMII)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Input Pulldown Fixed 20 µA
Pulldown		 RMII carrier sense and data valid
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 107 RMII synchronous reference clock for receive, transmit and control interface
AD1EVT/MII_RX_ER/RMII_RX_ER 86 RMII receive error
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 RMII receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 Output Pullup None RMII transmit data
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99
MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 RMII transmit enable

Table 4-15 PGE Ethernet Controller: Media Independent Interface (MII)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/EQEP1S 130 Input Pullup None Collision detect
N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Pulldown Fixed 20 µA
Pulldown		 Carrier sense and receive data valid
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 107 I/O Pulldown None MII output receive clock
N2HET1[30]/MII_RX_DV/EQEP2S 127 Input Pulldown Fixed 20 µA
Pulldown		 Received data valid
AD1EVT/MII_RX_ER/RMII_RX_ER 86 Receive error
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 107 I/O Receive clock
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 Input Receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 96 Pullup Fixed 20 µA
Pulldown
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ ECAP5 97
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 118 I/O Pulldown None MII output transmit clock
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 118 Fixed 20 µA
Pulldown		 Transmit clock
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 Output Pullup None Transmit data
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] 99
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 105
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown
MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 Pullup Transmit enable

4.3.1.14 System Module Interface

Table 4-16 PGE System Module Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
nPORRST 46 Input Pulldown Fixed 100 µA
Pulldown		 Power-on reset, cold reset
External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter.
See Section 6.8.
nRST 116 I/O Pullup Fixed 100 µA
Pullup		 System reset, warm reset, bidirectional.
The internal circuitry indicates any reset condition by driving nRST low.
The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. See Section 6.8.
nERROR 117 I/O Pulldown Fixed 20 µA
Pulldown		 ESM Error Signal
Indicates error of high severity. See Section 6.18.

4.3.1.15 Clock Inputs and Outputs

Table 4-17 PGE Clock Inputs and Outputs

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
OSCIN 18 Input N/A None From external crystal/resonator, or external clock input
KELVIN_GND 19 Input Kelvin ground for oscillator
OSCOUT 20 Output To external crystal/resonator
ECLK 119 I/O Pulldown Programmable, 20 µA External prescaled clock output, or GPIO.
GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS 14 Input Pulldown Fixed 20 µA
Pulldown		 External clock input #1

4.3.1.16 Test and Debug Modules Interface

Table 4-18 PGE Test and Debug Modules Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
TEST 34 Input Pulldown Fixed 100 µA
Pulldown		 Test enable. This terminal must be connected to ground directly or via a pulldown resistor.
nTRST 109 Input JTAG test hardware reset
RTCK 113 Output N/A None JTAG return test clock
TCK 112 Input Pulldown Fixed 100 µA
Pulldown		 JTAG test clock
TDI 110 Input Pullup Fixed 100 µA
Pullup		 JTAG test data in
TDO 111 Output 100 µA Pulldown None JTAG test data out
TMS 108 Input Pullup Fixed 100 µA
Pullup		 JTAG test select

4.3.1.17 Flash Supply and Test Pads

Table 4-19 PGE Flash Supply and Test Pads

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VCCP 134 3.3V Power N/A None Flash pump supply
FLTP1 7 - N/A- None Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2 8

4.3.1.18 Supply for Core Logic: 1.2V nominal

Table 4-20 PGE Supply for Core Logic: 1.2V nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VCC 17 1.2V Power N/A None Core supply
VCC 29
VCC 45
VCC 48
VCC 49
VCC 57
VCC 87
VCC 101
VCC 114
VCC 123
VCC 137
VCC 143

4.3.1.19 Supply for I/O Cells: 3.3V nominal

Table 4-21 PGE Supply for I/O Cells: 3.3V nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VCCIO 10 3.3V Power N/A None Operating supply for I/Os
VCCIO 26
VCCIO 42
VCCIO 104
VCCIO 120
VCCIO 136

4.3.1.20 Ground Reference for All Supplies Except VCCAD

Table 4-22 PGE Ground Reference for All Supplies Except VCCAD

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 144 PGE
VSS 11 Ground N/A None Ground reference
VSS 21
VSS 27
VSS 28
VSS 43
VSS 44
VSS 47
VSS 50
VSS 56
VSS 88
VSS 102
VSS 103
VSS 115
VSS 121
VSS 122
VSS 135
VSS 138
VSS 144

4.3.2 ZWT Package

4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)

Table 4-23 ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
ADREFHI(1) V15 Power N/A None ADC high reference supply
ADREFLO(1) V16 Power ADC low reference supply
VCCAD(1) W15 Power Operating supply for ADC
VSSAD V19 Ground N/A None ADC supply power
VSSAD W16
VSSAD W18
VSSAD W19
AD1EVT/MII_RX_ER/RMII_RX_ER N19 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 V10 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO
AD1IN[0] W14 Input N/A None ADC1 analog input
AD1IN[1] V17
AD1IN[2] V18
AD1IN[3] T17
AD1IN[4] U18
AD1IN[5] R17
AD1IN[6] T19
AD1IN[7] V14
AD1IN[8] / AD2IN[8] P18 Input N/A None ADC1/ADC2 shared analog inputs
AD1IN[9] / AD2IN[9] W17
AD1IN[10] / AD2IN[10] U17
AD1IN[11] / AD2IN[11] U19
AD1IN[12] / AD2IN[12] T16
AD1IN[13] / AD2IN[13] T18
AD1IN[14] / AD2IN[14] R18
AD1IN[15] / AD2IN[15] P19
AD1IN[16] / AD2IN[0] V13
AD1IN[17] / AD2IN[1] U13
AD1IN[18] / AD2IN[2] U14
AD1IN[19] / AD2IN[3] U16
AD1IN[20] / AD2IN[4] U15
AD1IN[21] / AD2IN[5] T15
AD1IN[22] / AD2IN[6] R19
AD1IN[23] / AD2IN[7] R16
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 Output Pullup None AWM1 external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 AWM1 external analog mux select line0
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 AWM1 external analog mux select line0
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

4.3.2.2 Enhanced High-End Timer Modules (N2HET)

Table 4-24 ZWT Enhanced High-End Timer Modules (N2HET)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
N2HET1[0]/SPI4CLK/EPWM2B K18 I/O Pulldown Programmable, 20 µA

N2HET1 time input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A V2
N2HET1[2]/SPI4SIMO[0]/EPWM3A W5
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1
N2HET1[4]/EPWM4B B12
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6
N2HET1[6]/SCIRX/EPWM5A W3
N2HET1[7]/N2HET2[14]/EPWM7B T1
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18
N2HET1[9]/N2HET2[16]/EPWM7A V7
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 D19
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3
N2HET1[12]/MII_CRS/RMII_CRS_DV B4
N2HET1[13]/SCITX/EPWM5B N2
N2HET1[14] A11
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4
N2HET1[17] A13
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ EQEP1S F3
N2HET1[18]/EPWM6A J1
N2HET1[19] B13
MIBSPI1NCS[2]/N2HET1[19]/MDIO G3
N2HET1[20]/EPWM6B P2
N2HET1[21] H4
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[22] B3
N2HET1[23] J4
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 G19 Pullup
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 Pulldown
N2HET1[25] M3
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14
N2HET1[27] A9
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 Pullup
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 K19 Pulldown
N2HET1[29] A3
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3
N2HET1[30]/MII_RX_DV/EQEP2S B11 I/O Pulldown Programmable, 20 µA
N2HET1[31] J17
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Pullup
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 input Pulldown Programmable, 20 µA(1) Disable selected PWM outputs
GIOA[2]/N2HET2[0] /EQEP2I C1 I/O Pulldown Programmable, 20 µA

N2HET2 time input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
EMIF_ADDR[0]/N2HET2[1] D4
GIOA[3]/N2HET2[2] E1
EMIF_ADDR[1]/N2HET2[3] D5
GIOA[6]/N2HET2[4]/EPWM1B H3
EMIF_BA[1]/N2HET2[5] D16
GIOA[7]/N2HET2[6]/EPWM2A M1
EMIF_nCS[0]/N2HET2[7] N17
N2HET1[1]/SPI4NENA/ N2HET2[8]/EQEP2A V2
EMIF_nCS[3]/N2HET2[9] K17
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1
EMIF_ADDR[6]/N2HET2[11] C4
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6
EMIF_ADDR[7]/N2HET2[13] C5
N2HET1[7]/N2HET2[14]/EPWM7B T1
EMIF_ADDR[8]/N2HET2[15] C6
N2HET1[9]/N2HET2[16]/EPWM7A V7
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 V10 I/O Pullup Programmable, 20 µA(1) Disable selected PWM outputs
(1) The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is controlled by the function which is selected by the output mux control for this terminal.

4.3.2.3 Enhanced Capture Modules (eCAP)

Table 4-25 ZWT Enhanced Capture Modules (eCAP)(1)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 I/O Pulldown Fixed 20 µA
Pullup		 Enhanced Capture Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 I/O Pullup Enhanced Capture Module 2 I/O
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 I/O Enhanced Capture Module 3 I/O
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 G19 I/O Enhanced Capture Module 4 I/O
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ ECAP5 H18 I/O Enhanced Capture Module 5 I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 I/O Enhanced Capture Module 6 I/O
(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-26 ZWT Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 Input Pullup Fixed 20 µA
Pullup		 Enhanced QEP1 Input A
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Input Enhanced QEP1 Input B
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 V10 I/O Enhanced QEP1 Index
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ EQEP1S F3 I/O Enhanced QEP1 Strobe
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A V2 Input Pulldown Enhanced QEP2 Input A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1 Input Pulldown Enhanced QEP2 Input B
GIOA[2]/N2HET2[0]/ EQEP2I C1 I/O Pulldown Enhanced QEP2 Index
N2HET1[30]/MII_RX_DV/EQEP2S B11 I/O Pulldown Enhanced QEP2 Strobe
(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-27 ZWT Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL SIGNAL TYPE Reset Pull State PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 Output Pulldown None Enhanced PWM1 Output A
GIOA[6]/N2HET2[4]/EPWM1B H3 Enhanced PWM1 Output B
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3 External ePWM Sync Pulse Output
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4 Input Fixed 20 µA
Pullup		 External ePWM Sync Pulse Input
GIOA[7]/N2HET2[6]/EPWM2A M1 Output None Enhanced PWM2 Output A
N2HET1[0]/SPI4CLK/EPWM2B K18 Enhanced PWM2 Output B
N2HET1[2]/SPI4SIMO[0]/EPWM3A W5 Enhanced PWM3 Output A
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6 Enhanced PWM3 Output B
MIBSPI5NCS[0]/EPWM4A E19 Pullup Enhanced PWM4 Output A
N2HET1[4]/EPWM4B B12 Pulldown Enhanced PWM4 Output B
N2HET1[6]/SCIRX/EPWM5A W3 Enhanced PWM5 Output A
N2HET1[13]/SCITX/EPWM5B N2 Enhanced PWM5 Output B
N2HET1[18]/EPWM6A J1 Enhanced PWM6 Output A
N2HET1[20]/EPWM6B P2 Enhanced PWM6 Output B
N2HET1[9]/N2HET2[16]/EPWM7A V7 Enhanced PWM7 Output A
N2HET1[7]/N2HET2[14]/EPWM7B T1 Enhanced PWM7 Output B
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 Input Pullup Fixed 20 µA
Pullup		 Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs.
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 D19 Pulldown

4.3.2.6 General-Purpose Input / Output (GPIO)

Table 4-28 ZWT General-Purpose Input / Output (GPIO)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
GIOA[0] A5 I/O Pulldown Programmable, 20 µA General-purpose I/O.
All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges.
GIOA[1] C2
GIOA[2]/N2HET2[0] /EQEP2I C1
GIOA[3]/N2HET2[2] E1
GIOA[4] A6
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5
GIOA[6]/N2HET2[4]/EPWM1B H3
GIOA[7]/N2HET2[6]/EPWM2A M1
GIOB[0] M2
GIOB[1] K2
GIOB[2] F2
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 V10(1)
GIOB[3] W10
GIOB[4] G1
GIOB[5] G2
GIOB[6] J2
GIOB[7] F1
(1) GIOB[2] cannot output a level on to terminal V10. Only the input functionality is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pullup is enabled on the input. This is not programmable using the GIO module control registers.

4.3.2.7 Controller Area Network Controllers (DCAN)

Table 4-29 ZWT Controller Area Network Controllers (DCAN)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
CAN1RX B10 I/O Pullup Programmable, 20 µA CAN1 receive, or GPIO
CAN1TX A10 CAN1 transmit, or GPIO
CAN2RX H1 CAN2 receive, or GPIO
CAN2TX H2 CAN2 transmit, or GPIO
CAN3RX M19 CAN3 receive, or GPIO
CAN3TX M18 CAN3 transmit, or GPIO

4.3.2.8 Local Interconnect Network Interface Module (LIN)

Table 4-30 ZWT Local Interconnect Network Interface Module (LIN)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
LINRX A7 I/O Pullup Programmable, 20 µA LIN receive, or GPIO
LINTX B7 LIN transmit, or GPIO

4.3.2.9 Standard Serial Communication Interface (SCI)

Table 4-31 ZWT Standard Serial Communication Interface (SCI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
N2HET1[6]/SCIRX/EPWM5A W3 I/O Pulldown Programmable, 20 µA SCI receive, or GPIO
N2HET1[13]/SCITX/EPWM5B N2 SCI transmit, or GPIO

4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)

Table 4-32 ZWT Inter-Integrated Circuit Interface Module (I2C)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 I/O Pullup Programmable, 20 µA I2C serial data, or GPIO
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 I2C serial clock, or GPIO

4.3.2.11 Standard Serial Peripheral Interface (SPI)

Table 4-33 ZWT Standard Serial Peripheral Interface (SPI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
SPI2CLK E2 I/O Pullup Programmable, 20 µA SPI2 clock, or GPIO
SPI2NCS[0] N3 SPI2 chip select, or GPIO
SPI2NENA/SPI2NCS[1] D3 SPI2 chip select, or GPIO
SPI2NENA/SPI2NCS[1] D3 SPI2 enable, or GPIO
SPI2SIMO[0] D1 SPI2 slave-input master-output, or GPIO
SPI2SOMI[0] D2 SPI2 slave-output master-input, or GPIO
N2HET1[0]/SPI4CLK/EPWM2B K18 I/O Pulldown Programmable, 20 µA SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A V2 SPI4 enable, or GPIO
N2HET1[2]/SPI4SIMO[0]/EPWM3A W5 SPI4 slave-input master-output, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6 SPI4 slave-output master-input, or GPIO

4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-34 ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
MIBSPI1CLK F18 I/O Pullup Programmable, 20 µA MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 MibSPI1 chip select, or GPIO
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/EQEP1S F3
MIBSPI1NCS[2]/N2HET1[19]/MDIO G3
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 Pulldown Programmable, 20 µA MibSPI1 chip select, or GPIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 G19 Pullup Programmable, 20 µA MibSPI1 enable, or GPIO
MIBSPI1SIMO[0] F19 MibSPI1 slave-in master-out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 Pulldown Programmable, 20 µA MibSPI1 slave-in master-out, or GPIO
MIBSPI1SOMI[0] G18 Pullup Programmable, 20 µA MibSPI1 slave-out master-in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 I/O Pullup Programmable, 20 µA MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS		 V10 MibSPI3 chip select, or GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3 Pulldown Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Pullup Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 MibSPI3 slave-in master-out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 MibSPI3 slave-out master-in, or GPIO
MIBSPI5CLK/MII_TXEN/RMII_TXEN H19 I/O Pullup Programmable, 20 µA MibSPI5 clock, or GPIO
MIBSPI5NCS[0]/EPWM4A E19 MibSPI5 chip select, or GPIO
MIBSPI5NCS[1] B6
MIBSPI5NCS[2] W6
MIBSPI5NCS[3] T12
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ECAP5 H18 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] J19 MibSPI5 slave-in master-out, or GPIO
MIBSPI5SIMO[1] E16
MIBSPI5SIMO[2] H17
MIBSPI5SIMO[3] G17
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 MibSPI5 slave-out master-in, or GPIO
MIBSPI5SOMI[1] E17
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ECAP5 H18
MIBSPI5SOMI[2] H16
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] J19
MIBSPI5SOMI[3] G16

4.3.2.13 Ethernet Controller

Table 4-35 ZWT Ethernet Controller: MDIO Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Output Pullup None Serial clock output
MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 I/O Pullup Fixed 20 µA
Pullup		 Serial data input/output

Table 4-36 ZWT Ethernet Controller: Reduced Media Independent Interface (RMII)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
N2HET1[12]/MII_CRS/RMII_CRS_DV B4 Input Pulldown Fixed 20 µA
Pulldown		 RMII carrier sense and receive data valid
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 K19 RMII synchronous reference clock for receive, transmit and control interface
AD1EVT/MII_RX_ER/RMII_RX_ER N19 RMII receive error
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 RMII receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 Output Pullup None RMII transmit data
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] J19
MIBSPI5CLK/MII_TXEN/RMII_TXEN H19 RMII transmit enable

Table 4-37 ZWT Ethernet Controller: Media Independent Interface (MII)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/EQEP1S F3 Input Pullup None Collision detect
N2HET1[12]/MII_CRS/RMII_CRS_DV B4 Pulldown Fixed 20 µA
Pulldown		 Carrier sense and receive data valid
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 K19 I/O Pulldown None MII output receive clock
N2HET1[30]/MII_RX_DV/EQEP2S B11 Input Pulldown Fixed 20 µA
Pulldown		 Received data valid
AD1EVT/MII_RX_ER/RMII_RX_ER N19 Receive error
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 K19 I/O Receive clock
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 Input Receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ECAP4 G19 Pullup Fixed 20 µA
Pulldown
MIBSPI5NENA/MII_RXD[3]/MIBSPI5SOMI[1]/ ECAP5 H18
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 D19 I/O Pulldown None MII output transmit clock
N2HET1[10]/MII_TXCLK/MII_TX_VCLKA4/nTZ3 D19 Fixed 20 µA
Pulldown		 Transmit clock
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 Output Pullup None Transmit data
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] J19
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 Pulldown
MIBSPI5CLK/MII_TXEN/RMII_TXEN H19 Pullup Transmit enable

4.3.2.14 External Memory Interface (EMIF)

Table 4-38 External Memory Interface (EMIF)

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
EMIF_CKE L3 Output Pullup None EMIF Clock Enable
EMIF_CLK K3 I/O None EMIF clock. This is an output signal in functional mode. It is gated off by default, so that the signal is pulled up. PINMUX29[8] must be cleared to enable this output.
EMIF_nOE E12 Output Pullup None EMIF Read Enable
EMIF_nWAIT P3 I/O Pullup Fixed 20 µA
Pullup		 EMIF Extended Wait Signal
EMIF_nWE D17 Output Pullup None EMIF Write Enable
EMIF_nCAS R4 Output EMIF column address strobe
EMIF_nRAS R3 Output EMIF row address strobe
EMIF_nCS[0]/N2HET2[7](1) N17 Output EMIF chip select, synchronous
EMIF_nCS[2] L17 Output EMIF chip selects, asynchronous
This applies to chip selects 2, 3 and 4
EMIF_nCS[3]/N2HET2[9](1) K17 Output
EMIF_nCS[4] M17 Output
EMIF_nDQM[0] E10 Output EMIF Data Mask or Write Strobe.
Data mask for SDRAM devices, write strobe for connected asynchronous devices.
EMIF_nDQM[1] E11 Output
EMIF_BA[0] E13 Output EMIF bank address or address line
EMIF_BA[1]/N2HET2[5](1) D16 Output EMIF bank address or address line
EMIF_ADDR[0]/N2HET2[1](1) D4 Output EMIF address
EMIF_ADDR[1]/N2HET2[3](1) D5 Output
EMIF_ADDR[2] E6 Output
EMIF_ADDR[3] E7 Output
EMIF_ADDR[4] E8 Output
EMIF_ADDR[5] E9 Output
EMIF_ADDR[6]/N2HET2[11](1) C4 Output
EMIF_ADDR[7]/N2HET2[13](1) C5 Output
EMIF_ADDR[8]/N2HET2[15](1) C6 Output
EMIF_ADDR[9] C7 Output
EMIF_ADDR[10] C8 Output
EMIF_ADDR[11] C9 Output
EMIF_ADDR[12] C10 Output
EMIF_DATA[0] K15 I/O Pullup Fixed 20 µA
Pullup		 EMIF Data
EMIF_DATA[1] L15 I/O
EMIF_DATA[2] M15 I/O
EMIF_DATA[3] N15 I/O
EMIF_DATA[4] E5 I/O
EMIF_DATA[5] F5 I/O
EMIF_DATA[6] G5 I/O
EMIF_DATA[7] K5 I/O
EMIF_DATA[8] L5 I/O
EMIF_DATA[9] M5 I/O
EMIF_DATA[10] N5 I/O
EMIF_DATA[11] P5 I/O
EMIF_DATA[12] R5 I/O
EMIF_DATA[13] R6 I/O
EMIF_DATA[14] R7 I/O
EMIF_DATA[15] R8 I/O
(1) These signals are tri-stated and pulled up by default after power-up. Any application that requires the EMIF must set the bit 31 of the system module general-purpose register GPREG1.

4.3.2.15 System Module Interface

Table 4-39 ZWT System Module Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
nPORRST W7 Input Pulldown Fixed 100 µA
Pulldown		 Power-on reset, cold reset
External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter.
See Section 6.8.
nRST B17 I/O Pullup Fixed 100 µA
Pullup		 System reset, warm reset, bidirectional.
The internal circuitry indicates any reset condition by driving nRST low.
The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. See Section 6.8.
nERROR B14 I/O Pulldown Fixed 20 µA
Pulldown		 ESM Error Signal
Indicates error of high severity. See Section 6.18.

4.3.2.16 Clock Inputs and Outputs

Table 4-40 ZWT Clock Inputs and Outputs

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
OSCIN K1 Input N/A None From external crystal/resonator, or external clock input
KELVIN_GND L2 Input Kelvin ground for oscillator
OSCOUT L1 Output To external crystal/resonator
ECLK A12 I/O Pulldown Programmable, 20 µA External prescaled clock output, or GIO.
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 Input Pulldown 20 µA External clock input #1
EXTCLKIN2 R9 Input External clock input #2
VCCPLL P11 1.2V Power N/A None Dedicated core supply for PLL's

4.3.2.17 Test and Debug Modules Interface

Table 4-41 ZWT Test and Debug Modules Interface

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
TEST U2 Input Pulldown Fixed 100 µA
Pulldown		 Test enable. This terminal must be connected to ground directly or via a pulldown resistor.
nTRST D18 Input JTAG test hardware reset
RTCK A16 Output N/A None JTAG return test clock
TCK B18 Input Pulldown Fixed 100 µA
Pulldown		 JTAG test clock
TDI A17 Input Pullup Fixed 100 µA
Pullup		 JTAG test data in
TDO C18 Output 100 µA Pulldown None JTAG test data out
TMS C19 Input Pullup Fixed 100 µA
Pullup		 JTAG test select

4.3.2.18 Flash Supply and Test Pads

Table 4-42 ZWT Flash Supply and Test Pads

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
VCCP F8 3.3V Power N/A None Flash pump supply
FLTP1 J5 - N/A None Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2 H5

4.3.2.19 Reserved

Table 4-43 Reserved

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
Reserved A15 - N/A None Reserved. These balls are connected to internal logic but are not outputs nor do they have internal pulls. They are subject to ±1 µA leakage current.
Reserved B15 - N/A None
Reserved B16 - N/A None
Reserved A8 - N/A- None
Reserved B8 - N/A None
Reserved B9 - N/A None

4.3.2.20 No Connects

Table 4-44 No Connects

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
NC C11 - N/A None No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.
NC C12 - N/A None
NC C13 - N/A None
NC C14 - N/A None
NC C15 - N/A None
NC C16 - N/A None
NC C17 - N/A None
NC D6 - N/A None
NC D7 - N/A None
NC D8 - N/A None
NC D9 - N/A None
NC D10 - N/A None
NC D11 - N/A None
NC D12 - N/A None
NC D13 - N/A None
NC D14 - N/A None
NC D15 - N/A None
NC E4 - N/A None
NC E14 - N/A None
NC E15 - N/A None
NC F4 - N/A None
NC F15 - N/A None
NC F16 - N/A None
NC F17 - N/A None
NC G4 - N/A None
NC G15 - N/A None
NC H15 - N/A None
NC J15 - N/A None
NC J16 - N/A None
NC K4 - N/A None
NC K16 - N/A None
NC L4 - N/A None
NC L16 - N/A None
NC L18 - N/A None
NC L19 - N/A None
NC M4 - N/A None
NC M16 - N/A None
NC N4 - N/A None
NC N16 - N/A None
NC N18 - N/A None
NC P4 - N/A None
NC P15 - N/A None No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.
NC P16 - N/A None
NC P17 - N/A None
NC R1 - N/A None
NC R10 - N/A None
NC R11 - N/A None
NC R12 - N/A None
NC R13 - N/A None
NC R14 - N/A None
NC R15 - N/A None
NC T2 - N/A None
NC T3 - N/A None
NC T4 - N/A None
NC T5 - N/A None
NC T6 - N/A None
NC T7 - N/A None
NC T8 - N/A None
NC T9 - N/A None
NC T10 - N/A None
NC T11 - N/A None
NC T13 - N/A None
NC T14 - N/A None
NC U3 - N/A- None
NC U4 - N/A None
NC U5 - N/A None
NC U6 - N/A None
NC U7 - N/A None
NC U8 - N/A None
NC U9 - N/A None
NC U10 - N/A None
NC U11 - N/A None
NC U12 - N/A None
NC V3 - N/A None
NC V4 - N/A None
NC V11 - N/A None
NC V12 - N/A None
NC W4 - N/A None
NC W11 - N/A None
NC W12 - N/A None
NC W13 - N/A None

4.3.2.21 Supply for Core Logic: 1.2V nominal

Table 4-45 ZWT Supply for Core Logic: 1.2V nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
VCC F9 1.2V Power N/A None Core supply
VCC F10
VCC H10
VCC J14
VCC K6
VCC K8
VCC K12
VCC K14
VCC L6
VCC M10
VCC P10

4.3.2.22 Supply for I/O Cells: 3.3V nominal

Table 4-46 ZWT Supply for I/O Cells: 3.3V nominal

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
VCCIO F6 3.3V Power N/A None Operating supply for I/Os
VCCIO F7
VCCIO F11
VCCIO F12
VCCIO F13
VCCIO F14
VCCIO G6
VCCIO G14
VCCIO H6
VCCIO H14
VCCIO J6
VCCIO L14
VCCIO M6
VCCIO M14
VCCIO N6
VCCIO N14
VCCIO P6
VCCIO P7
VCCIO P8
VCCIO P9
VCCIO P12
VCCIO P13
VCCIO P14

4.3.2.23 Ground Reference for All Supplies Except VCCAD

Table 4-47 ZWT Ground Reference for All Supplies Except VCCAD

Terminal Signal Type Reset Pull State Pull Type Description
Signal Name 337 ZWT
VSS A1 Ground N/A None Ground reference
VSS A2
VSS A18
VSS A19
VSS B1
VSS B19
VSS H8
VSS H9
VSS H11
VSS H12
VSS J8
VSS J9
VSS J10
VSS J11
VSS J12
VSS K9
VSS K10
VSS K11
VSS L8
VSS L9
VSS L10
VSS L11
VSS L12
VSS M8
VSS M9
VSS M11
VSS M12
VSS V1
VSS W1
VSS W2