Refer to the PDF data sheet for device specific package drawings
The RM46Lx50 device is a high-performance microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The RM46Lx50 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and can run up to 200 MHz providing up to 332 DMIPS. The device supports the little-endian [LE] format.
The RM46L850 device has 1.25MB of integrated flash and 192KB of data RAM with single-bit error correction and double-bit error detection. The RM46L450 device has 1MB of integrated flash and 128KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 200 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range.
The RM46Lx50 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors with up to 44 I/O terminals, seven Enhanced Pulse Width Modulator (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.
The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and it supports both high-side and low-side PWM and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM module is ideal for digital motor control applications.
The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM generation when the eCAP is not needed for capture applications.
The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.
The device has two12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. Each MibADC supports three separate groupings of channels. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired. MibADC1 also supports the use of external analog multiplexers.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, one I2C, one Ethernet, and one USB module. The SPI provides a convenient method of serial high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The Ethernet module supports MII, RMII, and MDIO interfaces.
The USB module includes a 2-port USB host controller that is revision 2.0-compatible, based on the OHCI specification for USB, release 1.0. The USB module also includes a USB device controller compatible with the USB specification revision 2.0 and USB specification revision 1.1.
The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.
A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the mapping between the available clock sources and the device clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.
The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or external error pin (ball) is triggered when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous memories or other slave devices.
A Parameter Overlay Module (POM) enhances the calibration capabilities of application code. The POM can reroute flash accesses to internal memory or to the EMIF, thus avoiding the reprogramming steps necessary for parameter updates in flash.
With integrated safety features and a wide choice of communication and control peripherals, the RM46Lx50 device is an ideal solution for high-performance real-time control applications with safety-critical requirements.
NOTE
The block diagram reflects the 337BGA package. Some pins are multiplexed or not available in the 144QFP. For details, see the respective terminal functions tables in Section 4.3.
This data manual revision history highlights the technical changes made to the SPNS184B device-specific data manual to make it an SPNS184C revision.
Scope: Applicable updates to the Hercules™ RM MCU device family, specifically relating to the RM46Lx50 devices, which are now in the production data (PD) stage of development have been incorporated.
Changes from March 14, 2015 to June 30, 2015 (from B Revision (March 2015) to C Revision)
Table 3-1 lists the features of the RM46Lx50 devices.
FEATURES | DEVICES | |||||||
---|---|---|---|---|---|---|---|---|
Generic Part Number | RM48L952ZWT(1) | RM46L852ZWT(1) | RM46L850ZWT | RM46L850PGE | RM46L450ZWT | RM46L450PGE | RM44L520PGE | RM42L432PZ |
Package | 337 BGA | 337 BGA | 337 BGA | 144 QFP | 337 BGA | 144 QFP | 144 QFP | 100 QFP |
CPU | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4 |
Frequency (MHz) | 220 | 220 | 200 | 200 | 200 | 200 | 200 | 100 |
Flash (KB) | 3072 | 1280 | 1280 | 1280 | 1024 | 1024 | 768 | 384 |
RAM (KB) | 256 | 192 | 192 | 192 | 128 | 128 | 128 | 32 |
Data Flash [EEPROM] (KB) | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 16 |
USB OHCI + Device | 2+0 or 1+1 | 2+0 or 1+1 | 2+0 or 1+1 | 2+0 or 1+1 | 2+0 or 1+1 | 2+0 or 1+1 | – | – |
EMAC | 10/100 | 10/100 | 10/100 | 10/100 | 10/100 | 10/100 | – | – |
CAN | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 2 |
MibADC 12-bit (Ch) |
2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 1 (16ch) |
N2HET (Ch) | 2 (44) | 2 (44) | 2 (44) | 2 (40) | 2 (44) | 2 (40) | 2 (40) | 1 (19) |
ePWM Channels | – | 14 | 14 | 14 | 14 | 14 | 14 | – |
eCAP Channels | – | 6 | 6 | 6 | 6 | 6 | 6 | – |
eQEP Channels | – | 2 | 2 | 2 | 2 | 2 | 2 | 1 |
MibSPI (CS) | 3 (6 + 6 + 4) | 3 (6 + 6 + 4) | 3 (6 + 6 + 4) | 3 (5 + 6 + 1) | 3 (6 + 6 + 4) | 3 (5 + 6 + 1) | 3 (5 + 6 + 1) | 1 (4) |
SPI (CS) | 2 (2 + 1) | 2 (2 + 1) | 2 (2 + 1) | 1 (1) | 2 (2 + 1) | 1 (1) | 1 (1) | 2 (4 + 4) |
SCI (LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 1(with LIN) |
I2C | 1 | 1 | 1 | 1 | 1 | 1 | 1 | – |
GPIO (INT)(4) | 144 (with 16 interrupt capable) | 101 (with 16 interrupt capable) | 101 (with 16 interrupt capable) | 64 (with 10 interrupt capable) | 101 (with 16 interrupt capable) | 64 (with 10 interrupt capable) | 64 (with 10 interrupt capable) | 45 (with 8 interrupt capable) |
EMIF | 16-bit data | 16-bit data | 16-bit data | – | 16-bit data | – | – | – |
ETM [Trace] (Data) | (32) | – | – | – | – | – | – | – |
RTP/DMM (Data) | (16/16) | – | – | – | – | – | – | – |
Operating Temperature |
-40ºC to 105ºC | -40ºC to 105ºC | -40ºC to 105ºC | -40ºC to 105ºC | -40ºC to 105ºC | -40ºC to 105ºC | -40ºC to 105ºC | -40ºC to 105ºC |
Core Supply (V) | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V |
I/O Supply (V) | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V |
Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.
Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.
Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a functional pin/ball description. The first signal name listed is the primary function for that terminal. The signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) chapter of the RM46x Technical Reference Manual (SPNU514).
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
ADREFHI(1) | 66 | Power | N/A | None | ADC high reference supply |
ADREFLO(1) | 67 | Power | ADC low reference supply | ||
VCCAD(1) | 69 | Power | Operating supply for ADC | ||
VSSAD(1) | 68 | Ground | |||
AD1EVT/MII_RX_ER/RMII_RX_ER | 86 | I/O | Pulldown | Programmable, 20 µA | ADC1 event trigger input, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
55 | I/O | Pullup | Programmable, 20 µA | ADC2 event trigger input, or GPIO |
AD1IN[0] | 60 | Input | N/A | None | ADC1 analog input |
AD1IN[1] | 71 | ||||
AD1IN[2] | 73 | ||||
AD1IN[3] | 74 | ||||
AD1IN[4] | 76 | ||||
AD1IN[5] | 78 | ||||
AD1IN[6] | 80 | ||||
AD1IN[7] | 61 | ||||
AD1IN[8] / AD2IN[8] | 83 | Input | N/A | None | ADC1/ADC2 shared analog inputs |
AD1IN[9] / AD2IN[9] | 70 | ||||
AD1IN[10] / AD2IN[10] | 72 | ||||
AD1IN[11] / AD2IN[11] | 75 | ||||
AD1IN[12] / AD2IN[12] | 77 | ||||
AD1IN[13] / AD2IN[13] | 79 | ||||
AD1IN[14] / AD2IN[14] | 82 | ||||
AD1IN[15] / AD2IN[15] | 85 | ||||
AD1IN[16] / AD2IN[0] | 58 | ||||
AD1IN[17] / AD2IN[1] | 59 | ||||
AD1IN[18] / AD2IN[2] | 62 | ||||
AD1IN[19] / AD2IN[3] | 63 | ||||
AD1IN[20] / AD2IN[4] | 64 | ||||
AD1IN[21] / AD2IN[5] | 65 | ||||
AD1IN[22] / AD2IN[6] | 81 | ||||
AD1IN[23] / AD2IN[7] | 84 | ||||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | 51 | Output | Pullup | None | AWM1 external analog mux enable |
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | 52 | Output | Pullup | None | AWM1 external analog mux select line0 |
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | 53 | Output | Pullup | None | AWM1 external analog mux select line0 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[0]/SPI4CLK/EPWM2B | 25 | I/O | Pulldown | Programmable, 20 µA |
N2HET1 time input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. |
N2HET1[1]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO/N2HET2[8]/EQEP2A |
23 | ||||
N2HET1[2]/SPI4SIMO[0]/EPWM3A | 30 | ||||
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
24 | ||||
N2HET1[4]/EPWM4B | 36 | ||||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | 31 | ||||
N2HET1[6]/SCIRX/EPWM5A | 38 | ||||
N2HET1[7]/USB2.PORTPOWER/USB_FUNC.GZO/ N2HET2[14]/EPWM7B |
33 | ||||
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]/ USB1.OVERCURRENT |
106 | ||||
N2HET1[9]/N2HET2[16]/USB2.SUSPEND/ USB_FUNC.SUSPENDO/EPWM7A |
35 | ||||
N2HET1[10]/MII_TXCLK/USB1.TXEN /MII_TX_VCLKA4/nTZ3 |
118 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ USB2.OVERCURRENT/USB_FUNC.VBUSI/ EPWM1SYNCO |
6 | ||||
N2HET1[12]/MII_CRS/RMII_CRS_DV | 124 | ||||
N2HET1[13]/SCITX/EPWM5B | 39 | ||||
N2HET1[14]/USB1.TXSE0 | 125 | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | 41 | ||||
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO | 139 | ||||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ USB1.SUSPEND/EQEP1S |
130 | Pullup | |||
N2HET1[18]/EPWM6A | 140 | Pulldown | |||
MIBSPI1NCS[2]/N2HET1[19]/MDIO | 40 | Pullup | |||
N2HET1[20]/EPWM6B | 141 | Pulldown | |||
N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O | 15 | ||||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ USB1.VP/ECAP4 |
96 | Pullup | |||
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] | 91 | Pulldown | |||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | 37 | Pullup | |||
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] | 92 | Pulldown | |||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 | 4 | Pullup | |||
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 | 107 | Pulldown | |||
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 | 3 | Pullup | |||
N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S | 127 | Pulldown | |||
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | Pullup | |||
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS | 14 | I/O | Pulldown | Programmable, 20 µA(1) | Disable selected PWM outputs |
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/ EQEP2I |
9 | I/O | Pulldown | Programmable, 20 µA |
N2HET2 time input capture or output compare, or GPIO Each terminal has a suppression filter with a programmable duration. |
GIOA[6]/N2HET2[4]/EPWM1B | 16 | ||||
GIOA[7]/N2HET2[6]/EPWM2A | 22 | ||||
N2HET1[1]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO/N2HET2[8]/EQEP2A |
23 | ||||
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
24 | ||||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | 31 | ||||
N2HET1[7]/USB2.PORTPOWER/USB_FUNC.GZO/ N2HET2[14]/EPWM7B |
33 | ||||
N2HET1[9]/N2HET2[16]/USB2.SUSPEND/ USB_FUNC.SUSPENDO/EPWM7A |
35 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ USB2.OVERCURRENT/USB_FUNC.VBUSI/ EPWM1SYNCO |
6 | ||||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
55 | I/O | Pullup | Programmable, 20 µA(1) | Disable selected PWM outputs |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | 41 | I/O | Pulldown | Fixed 20 µA Pullup |
Enhanced Capture Module 1 I/O |
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | 51 | Pullup | Enhanced Capture Module 2 I/O | ||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | 52 | Enhanced Capture Module 3 I/O | |||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ USB1.VP/ECAP4 |
96 | Enhanced Capture Module 4 I/O | |||
MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ ECAP5 |
97 | Enhanced Capture Module 5 I/O | |||
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ USB1.RCV/ECAP6 |
105 | Enhanced Capture Module 6 I/O |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | 53 | Input | Pullup | Fixed 20 µA Pullup |
Enhanced QEP1 Input A |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | Input | Enhanced QEP1 Input B | ||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
55 | I/O | Enhanced QEP1 Index | ||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
/USB1.SUSPEND /EQEP1S |
130 | I/O | Enhanced QEP1 Strobe | ||
N2HET1[1]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO/N2HET2[8]/EQEP2A |
23 | Input | Pulldown | Enhanced QEP2 Input A | |
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
24 | Input | Enhanced QEP2 Input B | ||
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/ EQEP2I |
9 | I/O | Enhanced QEP2 Index | ||
N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S | 127 | I/O | Enhanced QEP2 Strobe |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
GIOA[0]/USB2.VP/USB_FUNC.RXDPI | 2 | I/O | Pulldown | Programmable, 20 µA | General-purpose I/O. All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges. |
GIOA[1]/USB2.VM/USB_FUNC.RXDMI | 5 | ||||
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]
/EQEP2I |
9 | ||||
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS | 14 | ||||
GIOA[6]/N2HET2[4]/EPWM1B | 16 | ||||
GIOA[7]/N2HET2[6]/EPWM2A | 22 | ||||
GIOB[0]/USB1.TXDAT | 126 | ||||
GIOB[1]/USB1.PORTPOWER | 133 | ||||
GIOB[2] | 142 | ||||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
55(1) | Pullup | |||
GIOB[3]/USB2.RCV/USB_FUNC.RXDI | 1 | Pulldown |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
CAN1RX | 90 | I/O | Pullup | Programmable, 20 µA | CAN1 receive, or GPIO |
CAN1TX | 89 | CAN1 transmit, or GPIO | |||
CAN2RX | 129 | CAN2 receive, or GPIO | |||
CAN2TX | 128 | CAN2 transmit, or GPIO | |||
CAN3RX | 12 | CAN3 receive, or GPIO | |||
CAN3TX | 13 | CAN3 transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
LINRX | 131 | I/O | Pullup | Programmable, 20 µA | LIN receive, or GPIO |
LINTX | 132 | LIN transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[6]/SCIRX/EPWM5A | 38 | I/O | Pulldown | Programmable, 20 µA | SCI receive, or GPIO |
N2HET1[13]/SCITX/EPWM5B | 39 | SCI transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 | 4 | I/O | Pullup | Programmable, 20 µA | I2C serial data, or GPIO |
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 | 3 | I2C serial clock, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[0]/SPI4CLK/EPWM2B | 25 | I/O | Pulldown | Programmable, 20 µA | SPI4 clock, or GPIO |
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
24 | SPI4 chip select, or GPIO | |||
N2HET1[1]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO/N2HET2[8]/EQEP2A |
23 | SPI4 enable, or GPIO | |||
N2HET1[2]/SPI4SIMO[0]/EPWM3A | 30 | SPI4 slave-input master-output, or GPIO | |||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | 31 | SPI4 slave-output master-input, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI1CLK | 95 | I/O | Pullup | Programmable, 20 µA | MibSPI1 clock, or GPIO |
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ USB1.RCV/ECAP6 |
105 | MibSPI1 chip select, or GPIO | |||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
/USB1.SUSPEND /EQEP1S |
130 | ||||
MIBSPI1NCS[2]/N2HET1[19]/MDIO | 40 | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | 41 | Pulldown | Programmable, 20 µA | MibSPI1 chip select, or GPIO | |
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] | 91 | ||||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ USB1.VP/ECAP4 |
96 | Pullup | Programmable, 20 µA | MibSPI1 enable, or GPIO | |
MIBSPI1SIMO[0] | 93 | MibSPI1 slave-in master-out, or GPIO | |||
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]/ USB1.OVERCURRENT |
106 | Pulldown | Programmable, 20 µA | MibSPI1 slave-in master-out, or GPIO | |
MIBSPI1SOMI[0] | 94 | Pullup | Programmable, 20 µA | MibSPI1 slave-out master-in, or GPIO | |
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ USB1.RCV/ECAP6 |
105 | ||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | 53 | I/O | Pullup | Programmable, 20 µA | MibSPI3 clock, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
55 | MibSPI3 chip select, or GPIO | |||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | 37 | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 | 4 | ||||
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 | 3 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ USB2.OVERCURRENT/USB_FUNC.VBUSI/EPWM1SYNCO |
6 | Pulldown | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | Pullup | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | 54 | MibSPI3 enable, or GPIO | |||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | 52 | MibSPI3 slave-in master-out, or GPIO | |||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | 51 | MibSPI3 slave-out master-in, or GPIO | |||
MIBSPI5CLK/MII_TXEN/RMII_TXEN | 100 | I/O | Pullup | Programmable, 20 µA | MibSPI5 clock, or GPIO |
MIBSPI5NCS[0]/EPWM4A | 32 | MibSPI5 chip select, or GPIO | |||
MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ ECAP5 |
97 | MibSPI5 enable, or GPIO | |||
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] | 99 | MibSPI5 slave-in master-out, or GPIO | |||
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] | 98 | MibSPI5 slave-out master-in, or GPIO | |||
MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ ECAP5 |
97 | MibSPI5 slave-out master-in, or GPIO | |||
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] | 99 | MibSPI5 slave-out master-in, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | 37 | Output | Pullup | None | Serial clock output |
MIBSPI1NCS[2]/N2HET1[19]/MDIO | 40 | I/O | Pullup | Fixed 20 µA Pullup |
Serial data input/output |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
N2HET1[12]/MII_CRS/RMII_CRS_DV | 124 | Input | Pulldown | Fixed 20 µA Pulldown |
RMII carrier sense and data valid |
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 | 107 | RMII synchronous reference clock for receive, transmit and control interface | |||
AD1EVT/MII_RX_ER/RMII_RX_ER | 86 | RMII receive error | |||
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] | 91 | RMII receive data | |||
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] | 92 | ||||
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] | 98 | Output | Pullup | None | RMII transmit data |
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] | 99 | ||||
MIBSPI5CLK/MII_TXEN/RMII_TXEN | 100 | RMII transmit enable |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ USB1.SUSPEND/EQEP1S |
130 | Input | Pullup | None | Collision detect |
N2HET1[12]/MII_CRS/RMII_CRS_DV | 124 | Pulldown | Fixed 20 µA Pulldown |
Carrier sense and receive data valid | |
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 | 107 | I/O | Pulldown | None | MII output receive clock |
N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S | 127 | Input | Pulldown | Fixed 20 µA Pulldown |
Received data valid |
AD1EVT/MII_RX_ER/RMII_RX_ER | 86 | Receive error | |||
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 | 107 | I/O | Receive clock | ||
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] | 91 | Input | Receive data | ||
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] | 92 | ||||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ USB1.VP/ECAP4 |
96 | Pullup | Fixed 20 µA Pulldown |
||
MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ ECAP5 |
97 | ||||
N2HET1[10]/MII_TXCLK/USB1.TXEN/ MII_TX_VCLKA4/nTZ3 |
118 | I/O | Pulldown | None | MII output transmit clock |
N2HET1[10]/MII_TXCLK/USB1.TXEN /MII_TX_VCLKA4/nTZ3 |
118 | Fixed 20 µA Pulldown |
Transmit clock | ||
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] | 98 | Output | Pullup | None | Transmit data |
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] | 99 | ||||
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ USB1.RCV/ECAP6 |
105 | ||||
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]/ USB1.OVERCURRENT |
106 | Pulldown | |||
MIBSPI5CLK/MII_TXEN/RMII_TXEN | 100 | Pullup | Transmit enable |
The USB Host Controller includes a root hub with two ports. USB1 pins are for Root Hub Port 0. USB2 pins are for Root Hub Port 1.
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
nPORRST | 46 | Input | Pulldown | Fixed 100 µA Pulldown |
Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8. |
nRST | 116 | I/O | Pullup | Fixed 100 µA Pullup |
System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8. |
nERROR | 117 | I/O | Pulldown | Fixed 20 µA Pulldown |
ESM Error Signal Indicates error of high severity. See Section 6.18. |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
OSCIN | 18 | Input | N/A | None | From external crystal/resonator, or external clock input |
KELVIN_GND | 19 | Input | Kelvin ground for oscillator | ||
OSCOUT | 20 | Output | To external crystal/resonator | ||
ECLK | 119 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GPIO. |
GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS | 14 | Input | Pulldown | Fixed 20 µA Pulldown |
External clock input #1 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VCCP | 134 | 3.3V Power | N/A | None | Flash pump supply |
FLTP1 | 7 | - | N/A- | None | Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. |
FLTP2 | 8 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VCC | 17 | 1.2V Power | N/A | None | Core supply |
VCC | 29 | ||||
VCC | 45 | ||||
VCC | 48 | ||||
VCC | 49 | ||||
VCC | 57 | ||||
VCC | 87 | ||||
VCC | 101 | ||||
VCC | 114 | ||||
VCC | 123 | ||||
VCC | 137 | ||||
VCC | 143 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VCCIO | 10 | 3.3V Power | N/A | None | Operating supply for I/Os |
VCCIO | 26 | ||||
VCCIO | 42 | ||||
VCCIO | 104 | ||||
VCCIO | 120 | ||||
VCCIO | 136 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 144 PGE | ||||
VSS | 11 | Ground | N/A | None | Ground reference |
VSS | 21 | ||||
VSS | 27 | ||||
VSS | 28 | ||||
VSS | 43 | ||||
VSS | 44 | ||||
VSS | 47 | ||||
VSS | 50 | ||||
VSS | 56 | ||||
VSS | 88 | ||||
VSS | 102 | ||||
VSS | 103 | ||||
VSS | 115 | ||||
VSS | 121 | ||||
VSS | 122 | ||||
VSS | 135 | ||||
VSS | 138 | ||||
VSS | 144 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
ADREFHI(1) | V15 | Power | N/A | None | ADC high reference supply |
ADREFLO(1) | V16 | Power | ADC low reference supply | ||
VCCAD(1) | W15 | Power | Operating supply for ADC | ||
VSSAD | V19 | Ground | N/A | None | ADC supply power |
VSSAD | W16 | ||||
VSSAD | W18 | ||||
VSSAD | W19 | ||||
AD1EVT/MII_RX_ER/RMII_RX_ER | N19 | I/O | Pulldown | Programmable, 20 µA | ADC1 event trigger input, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
V10 | I/O | Pullup | Programmable, 20 µA | ADC2 event trigger input, or GPIO |
AD1IN[0] | W14 | Input | N/A | None | ADC1 analog input |
AD1IN[1] | V17 | ||||
AD1IN[2] | V18 | ||||
AD1IN[3] | T17 | ||||
AD1IN[4] | U18 | ||||
AD1IN[5] | R17 | ||||
AD1IN[6] | T19 | ||||
AD1IN[7] | V14 | ||||
AD1IN[8] / AD2IN[8] | P18 | Input | N/A | None | ADC1/ADC2 shared analog inputs |
AD1IN[9] / AD2IN[9] | W17 | ||||
AD1IN[10] / AD2IN[10] | U17 | ||||
AD1IN[11] / AD2IN[11] | U19 | ||||
AD1IN[12] / AD2IN[12] | T16 | ||||
AD1IN[13] / AD2IN[13] | T18 | ||||
AD1IN[14] / AD2IN[14] | R18 | ||||
AD1IN[15] / AD2IN[15] | P19 | ||||
AD1IN[16] / AD2IN[0] | V13 | ||||
AD1IN[17] / AD2IN[1] | U13 | ||||
AD1IN[18] / AD2IN[2] | U14 | ||||
AD1IN[19] / AD2IN[3] | U16 | ||||
AD1IN[20] / AD2IN[4] | U15 | ||||
AD1IN[21] / AD2IN[5] | T15 | ||||
AD1IN[22] / AD2IN[6] | R19 | ||||
AD1IN[23] / AD2IN[7] | R16 | ||||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | V8 | Output | Pullup | None | AWM1 external analog mux enable |
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | W8 | AWM1 external analog mux select line0 | |||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | V9 | AWM1 external analog mux select line0 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
N2HET1[0]/SPI4CLK/EPWM2B | K18 | I/O | Pulldown | Programmable, 20 µA |
N2HET1 time input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. |
N2HET1[1]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO/N2HET2[8]/EQEP2A |
V2 | ||||
N2HET1[2]/SPI4SIMO[0]/EPWM3A | W5 | ||||
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
U1 | ||||
N2HET1[4]/EPWM4B | B12 | ||||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | V6 | ||||
N2HET1[6]/SCIRX/EPWM5A | W3 | ||||
N2HET1[7]/USB2.PORTPOWER/ USB_FUNC.GZO/N2HET2[14]/EPWM7B |
T1 | ||||
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]/ USB1.OVERCURRENT |
E18 | ||||
N2HET1[9]/N2HET2[16]/ USB2.SUSPEND/USB_FUNC.SUSPENDO/EPWM7A |
V7 | ||||
N2HET1[10]/MII_TXCLK/ USB1.TXEN/MII_TX_VCLKA4/nTZ3 |
D19 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ USB2.OVERCURRENT/USB_FUNC.VBUSI/EPWM1SYNCO |
E3 | ||||
N2HET1[12]/MII_CRS/RMII_CRS_DV | B4 | ||||
N2HET1[13]/SCITX/EPWM5B | N2 | ||||
N2HET1[14]/USB1.TXSE0 | A11 | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | N1 | ||||
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO | A4 | ||||
N2HET1[17] | A13 | ||||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/USB1.SUSPEND/ EQEP1S |
F3 | ||||
N2HET1[18]/EPWM6A | J1 | ||||
N2HET1[19] | B13 | ||||
MIBSPI1NCS[2]/N2HET1[19]/MDIO | G3 | ||||
N2HET1[20]/EPWM6B | P2 | ||||
N2HET1[21] | H4 | ||||
MIBSPI1NCS[3]/N2HET1[21] | J3 | ||||
N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O | B3 | ||||
N2HET1[23] | J4 | ||||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ USB1.VP/ECAP4 |
G19 | Pullup | |||
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] | P1 | Pulldown | |||
N2HET1[25] | M3 | ||||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | V5 | ||||
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] | A14 | ||||
N2HET1[27] | A9 | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 | B2 | Pullup | |||
N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_VCLKA4 | K19 | Pulldown | |||
N2HET1[29] | A3 | ||||
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 | C3 | ||||
N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S | B11 | I/O | Pulldown | Programmable, 20 µA | |
N2HET1[31] | J17 | ||||
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | W9 | Pullup | |||
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS | B5 | input | Pulldown | Programmable, 20 µA(1) | Disable selected PWM outputs |
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]
/EQEP2I |
C1 | I/O | Pulldown | Programmable, 20 µA |
N2HET2 time input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. |
EMIF_ADDR[0]/N2HET2[1] | D4 | ||||
GIOA[3]/N2HET2[2] | E1 | ||||
EMIF_ADDR[1]/N2HET2[3] | D5 | ||||
GIOA[6]/N2HET2[4]/EPWM1B | H3 | ||||
EMIF_BA[1]/N2HET2[5] | D16 | ||||
GIOA[7]/N2HET2[6]/EPWM2A | M1 | ||||
EMIF_nCS[0]/N2HET2[7] | N17 | ||||
N2HET1[1]/SPI4NENA/USB2.TXEN/USB_FUNC.PUENO/ N2HET2[8]/EQEP2A |
V2 | ||||
EMIF_nCS[3]/N2HET2[9] | K17 | ||||
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
U1 | ||||
EMIF_ADDR[6]/N2HET2[11] | C4 | ||||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | V6 | ||||
EMIF_ADDR[7]/N2HET2[13] | C5 | ||||
N2HET1[7]/USB2.PORTPOWER/ USB_FUNC.GZO/N2HET2[14]/EPWM7B |
T1 | ||||
EMIF_ADDR[8]/N2HET2[15] | C6 | ||||
N2HET1[9]/N2HET2[16]/USB2.SUSPEND/ USB_FUNC.SUSPENDO/EPWM7A |
V7 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ USB2.OVERCURRENT/USB_FUNC.VBUSI/EPWM1SYNCO |
E3 | ||||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
V10 | I/O | Pullup | Programmable, 20 µA(1) | Disable selected PWM outputs |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | N1 | I/O | Pulldown | Fixed 20 µA Pullup |
Enhanced Capture Module 1 I/O |
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | V8 | I/O | Pullup | Enhanced Capture Module 2 I/O | |
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | W8 | I/O | Enhanced Capture Module 3 I/O | ||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/USB1.VP/ECAP4 | G19 | I/O | Enhanced Capture Module 4 I/O | ||
MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ ECAP5 |
H18 | I/O | Enhanced Capture Module 5 I/O | ||
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/USB1.RCV/
ECAP6 |
R2 | I/O | Enhanced Capture Module 6 I/O |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | V9 | Input | Pullup | Fixed 20 µA Pullup |
Enhanced QEP1 Input A |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | W9 | Input | Enhanced QEP1 Input B | ||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
V10 | I/O | Enhanced QEP1 Index | ||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/USB1.SUSPEND/ EQEP1S |
F3 | I/O | Enhanced QEP1 Strobe | ||
N2HET1[1]/SPI4NENA/USB2.TXEN/USB_FUNC.PUENO/ N2HET2[8]/EQEP2A |
V2 | Input | Pulldown | Enhanced QEP2 Input A | |
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENON/N2HET2[10]/EQEP2B | U1 | Input | Pulldown | Enhanced QEP2 Input B | |
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/ EQEP2I |
C1 | I/O | Pulldown | Enhanced QEP2 Index | |
N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S | B11 | I/O | Pulldown | Enhanced QEP2 Strobe |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
GIOA[0]/USB2.VP/USB_FUNC.RXDPI | A5 | I/O | Pulldown | Programmable, 20 µA | General-purpose I/O. All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges. |
GIOA[1]/USB2.VM/USB_FUNC.RXDMI | C2 | ||||
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0] /EQEP2I | C1 | ||||
GIOA[3]/N2HET2[2] | E1 | ||||
GIOA[4] | A6 | ||||
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS | B5 | ||||
GIOA[6]/N2HET2[4]/EPWM1B | H3 | ||||
GIOA[7]/N2HET2[6]/EPWM2A | M1 | ||||
GIOB[0]/USB1.TXDAT | M2 | ||||
GIOB[1]/USB1.PORTPOWER | K2 | ||||
GIOB[2] | F2 | ||||
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
V10(1) | ||||
GIOB[3]/USB2.RCV /USB_FUNC.RXDI | W10 | ||||
GIOB[4] | G1 | ||||
GIOB[5] | G2 | ||||
GIOB[6] | J2 | ||||
GIOB[7] | F1 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
CAN1RX | B10 | I/O | Pullup | Programmable, 20 µA | CAN1 receive, or GPIO |
CAN1TX | A10 | CAN1 transmit, or GPIO | |||
CAN2RX | H1 | CAN2 receive, or GPIO | |||
CAN2TX | H2 | CAN2 transmit, or GPIO | |||
CAN3RX | M19 | CAN3 receive, or GPIO | |||
CAN3TX | M18 | CAN3 transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
LINRX | A7 | I/O | Pullup | Programmable, 20 µA | LIN receive, or GPIO |
LINTX | B7 | LIN transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
N2HET1[6]/SCIRX/EPWM5A | W3 | I/O | Pulldown | Programmable, 20 µA | SCI receive, or GPIO |
N2HET1[13]/SCITX/EPWM5B | N2 | SCI transmit, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 | B2 | I/O | Pullup | Programmable, 20 µA | I2C serial data, or GPIO |
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 | C3 | I2C serial clock, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
SPI2CLK | E2 | I/O | Pullup | Programmable, 20 µA | SPI2 clock, or GPIO |
SPI2NCS[0] | N3 | SPI2 chip select, or GPIO | |||
SPI2NENA/SPI2NCS[1] | D3 | SPI2 chip select, or GPIO | |||
SPI2NENA/SPI2NCS[1] | D3 | SPI2 enable, or GPIO | |||
SPI2SIMO[0] | D1 | SPI2 slave-input master-output, or GPIO | |||
SPI2SOMI[0] | D2 | SPI2 slave-output master-input, or GPIO | |||
N2HET1[0]/SPI4CLK/EPWM2B | K18 | I/O | Pulldown | Programmable, 20 µA | SPI4 clock, or GPIO |
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ USB_FUNC.PUENON/N2HET2[10]/EQEP2B |
U1 | SPI4 chip select, or GPIO | |||
N2HET1[1]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO/N2HET2[8]/EQEP2A |
V2 | SPI4 enable, or GPIO | |||
N2HET1[2]/SPI4SIMO[0]/EPWM3A | W5 | SPI4 slave-input master-output, or GPIO | |||
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B | V6 | SPI4 slave-output master-input, or GPIO |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
MIBSPI1CLK | F18 | I/O | Pullup | Programmable, 20 µA | MibSPI1 clock, or GPIO |
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ USB1.RCV/ECAP6 |
R2 | MibSPI1 chip select, or GPIO | |||
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ USB1.SUSPEND /EQEP1S |
F3 | ||||
MIBSPI1NCS[2]/N2HET1[19]/MDIO | G3 | ||||
MIBSPI1NCS[3]/N2HET1[21] | J3 | ||||
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 | N1 | Pulldown | Programmable, 20 µA | MibSPI1 chip select, or GPIO | |
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] | P1 | ||||
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ USB1.VP/ECAP4 |
G19 | Pullup | Programmable, 20 µA | MibSPI1 enable, or GPIO | |
MIBSPI1SIMO[0] | F19 | MibSPI1 slave-in master-out, or GPIO | |||
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]/ USB1.OVERCURRENT |
E18 | Pulldown | Programmable, 20 µA | MibSPI1 slave-in master-out, or GPIO | |
MIBSPI1SOMI[0] | G18 | Pullup | Programmable, 20 µA | MibSPI1 slave-out master-in, or GPIO | |
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ USB1.RCV/ECAP6 |
R2 | ||||
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A | V9 | I/O | Pullup | Programmable, 20 µA | MibSPI3 clock, or GPIO |
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS |
V10 | MibSPI3 chip select, or GPIO | |||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | V5 | ||||
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 | B2 | ||||
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 | C3 | ||||
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ USB2.OVERCURRENT/USB_FUNC.VBUSI/EPWM1SYNCO |
E3 | Pulldown | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | W9 | Pullup | Programmable, 20 µA | MibSPI3 chip select, or GPIO | |
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B | W9 | MibSPI3 enable, or GPIO | |||
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 | W8 | MibSPI3 slave-in master-out, or GPIO | |||
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 | V8 | MibSPI3 slave-out master-in, or GPIO | |||
MIBSPI5CLK/MII_TXEN/RMII_TXEN | H19 | I/O | Pullup | Programmable, 20 µA | MibSPI5 clock, or GPIO |
MIBSPI5NCS[0]/EPWM4A | E19 | MibSPI5 chip select, or GPIO | |||
MIBSPI5NCS[1] | B6 | ||||
MIBSPI5NCS[2] | W6 | ||||
MIBSPI5NCS[3] | T12 | ||||
MIBSPI5NENA/MII_RXD[3]/ USB1.VM/MIBSPI5SOMI[1]/ECAP5 |
H18 | MibSPI5 enable, or GPIO | |||
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] | J19 | MibSPI5 slave-in master-out, or GPIO | |||
MIBSPI5SIMO[1] | E16 | ||||
MIBSPI5SIMO[2] | H17 | ||||
MIBSPI5SIMO[3] | G17 | ||||
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] | J18 | MibSPI5 slave-out master-in, or GPIO | |||
MIBSPI5SOMI[1] | E17 | ||||
MIBSPI5NENA/MII_RXD[3]/ USB1.VM/MIBSPI5SOMI[1]/ECAP5 |
H18 | ||||
MIBSPI5SOMI[2] | H16 | ||||
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]/MII_TXD[1]/RMII_TXD[1] | J19 | ||||
MIBSPI5SOMI[3] | G16 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
MIBSPI3NCS[1]/N2HET1[25]/MDCLK | V5 | Output | Pullup | None | Serial clock output |
MIBSPI1NCS[2]/N2HET1[19]/MDIO | G3 | I/O | Pullup | Fixed 20 µA Pullup |
Serial data input/output |
The USB Host Controller includes a root hub with two ports. USB1 pin are for Root Hub Port 0. USB2 pins are for Root Hub Port 1.
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
EMIF_CKE | L3 | Output | Pullup | None | EMIF Clock Enable |
EMIF_CLK | K3 | I/O | None | EMIF clock. This is an output signal in functional mode. It is gated off by default, so that the signal is pulled up. PINMUX29[8] must be cleared to enable this output. | |
EMIF_nOE | E12 | Output | Pullup | None | EMIF Read Enable |
EMIF_nWAIT | P3 | I/O | Pullup | Fixed 20 µA Pullup |
EMIF Extended Wait Signal |
EMIF_nWE | D17 | Output | Pullup | None | EMIF Write Enable |
EMIF_nCAS | R4 | Output | EMIF column address strobe | ||
EMIF_nRAS | R3 | Output | EMIF row address strobe | ||
EMIF_nCS[0]/N2HET2[7](1) | N17 | Output | EMIF chip select, synchronous | ||
EMIF_nCS[2] | L17 | Output | EMIF chip selects, asynchronous This applies to chip selects 2, 3 and 4 |
||
EMIF_nCS[3]/N2HET2[9](1) | K17 | Output | |||
EMIF_nCS[4] | M17 | Output | |||
EMIF_nDQM[0] | E10 | Output | EMIF Data Mask or Write Strobe. Data mask for SDRAM devices, write strobe for connected asynchronous devices. |
||
EMIF_nDQM[1] | E11 | Output | |||
EMIF_BA[0] | E13 | Output | EMIF bank address or address line | ||
EMIF_BA[1]/N2HET2[5](1) | D16 | Output | EMIF bank address or address line | ||
EMIF_ADDR[0]/N2HET2[1](1) | D4 | Output | EMIF address | ||
EMIF_ADDR[1]/N2HET2[3](1) | D5 | Output | |||
EMIF_ADDR[2] | E6 | Output | |||
EMIF_ADDR[3] | E7 | Output | |||
EMIF_ADDR[4] | E8 | Output | |||
EMIF_ADDR[5] | E9 | Output | |||
EMIF_ADDR[6]/N2HET2[11](1) | C4 | Output | |||
EMIF_ADDR[7]/N2HET2[13](1) | C5 | Output | |||
EMIF_ADDR[8]/N2HET2[15](1) | C6 | Output | |||
EMIF_ADDR[9] | C7 | Output | |||
EMIF_ADDR[10] | C8 | Output | |||
EMIF_ADDR[11] | C9 | Output | |||
EMIF_ADDR[12] | C10 | Output | |||
EMIF_DATA[0] | K15 | I/O | Pullup | Fixed 20 µA Pullup |
EMIF Data |
EMIF_DATA[1] | L15 | I/O | |||
EMIF_DATA[2] | M15 | I/O | |||
EMIF_DATA[3] | N15 | I/O | |||
EMIF_DATA[4] | E5 | I/O | |||
EMIF_DATA[5] | F5 | I/O | |||
EMIF_DATA[6] | G5 | I/O | |||
EMIF_DATA[7] | K5 | I/O | |||
EMIF_DATA[8] | L5 | I/O | |||
EMIF_DATA[9] | M5 | I/O | |||
EMIF_DATA[10] | N5 | I/O | |||
EMIF_DATA[11] | P5 | I/O | |||
EMIF_DATA[12] | R5 | I/O | |||
EMIF_DATA[13] | R6 | I/O | |||
EMIF_DATA[14] | R7 | I/O | |||
EMIF_DATA[15] | R8 | I/O |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
nPORRST | W7 | Input | Pulldown | Fixed 100 µA Pulldown |
Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8. |
nRST | B17 | I/O | Pullup | Fixed 100 µA Pullup |
System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8. |
nERROR | B14 | I/O | Pulldown | Fixed 20 µA Pulldown |
ESM Error Signal Indicates error of high severity. See Section 6.18. |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
OSCIN | K1 | Input | N/A | None | From external crystal/resonator, or external clock input |
KELVIN_GND | L2 | Input | Kelvin ground for oscillator | ||
OSCOUT | L1 | Output | To external crystal/resonator | ||
ECLK | A12 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GIO. |
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS | B5 | Input | Pulldown | 20 µA | External clock input #1 |
EXTCLKIN2 | R9 | Input | External clock input #2 | ||
VCCPLL | P11 | 1.2V Power | N/A | None | Dedicated core supply for PLL's |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
VCCP | F8 | 3.3V Power | N/A | None | Flash pump supply |
FLTP1 | J5 | - | N/A | None | Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. |
FLTP2 | H5 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
NC | C11 | - | N/A | None | No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device. |
NC | C12 | - | N/A | None | |
NC | C13 | - | N/A | None | |
NC | C14 | - | N/A | None | |
NC | C15 | - | N/A | None | |
NC | C16 | - | N/A | None | |
NC | C17 | - | N/A | None | |
NC | D6 | - | N/A | None | |
NC | D7 | - | N/A | None | |
NC | D8 | - | N/A | None | |
NC | D9 | - | N/A | None | |
NC | D10 | - | N/A | None | |
NC | D11 | - | N/A | None | |
NC | D12 | - | N/A | None | |
NC | D13 | - | N/A | None | |
NC | D14 | - | N/A | None | |
NC | D15 | - | N/A | None | |
NC | E4 | - | N/A | None | |
NC | E14 | - | N/A | None | |
NC | E15 | - | N/A | None | |
NC | F4 | - | N/A | None | |
NC | F15 | - | N/A | None | |
NC | F16 | - | N/A | None | |
NC | F17 | - | N/A | None | |
NC | G4 | - | N/A | None | |
NC | G15 | - | N/A | None | |
NC | H15 | - | N/A | None | |
NC | J15 | - | N/A | None | |
NC | J16 | - | N/A | None | |
NC | K4 | - | N/A | None | |
NC | K16 | - | N/A | None | |
NC | L4 | - | N/A | None | |
NC | L16 | - | N/A | None | |
NC | L18 | - | N/A | None | |
NC | L19 | - | N/A | None | |
NC | M4 | - | N/A | None | |
NC | M16 | - | N/A | None | |
NC | N4 | - | N/A | None | |
NC | N16 | - | N/A | None | |
NC | N18 | - | N/A | None | |
NC | P4 | - | N/A | None | |
NC | P15 | - | N/A | None | No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device. |
NC | P16 | - | N/A | None | |
NC | P17 | - | N/A | None | |
NC | R1 | - | N/A | None | |
NC | R10 | - | N/A | None | |
NC | R11 | - | N/A | None | |
NC | R12 | - | N/A | None | |
NC | R13 | - | N/A | None | |
NC | R14 | - | N/A | None | |
NC | R15 | - | N/A | None | |
NC | T2 | - | N/A | None | |
NC | T3 | - | N/A | None | |
NC | T4 | - | N/A | None | |
NC | T5 | - | N/A | None | |
NC | T6 | - | N/A | None | |
NC | T7 | - | N/A | None | |
NC | T8 | - | N/A | None | |
NC | T9 | - | N/A | None | |
NC | T10 | - | N/A | None | |
NC | T11 | - | N/A | None | |
NC | T13 | - | N/A | None | |
NC | T14 | - | N/A | None | |
NC | U3 | - | N/A- | None | |
NC | U4 | - | N/A | None | |
NC | U5 | - | N/A | None | |
NC | U6 | - | N/A | None | |
NC | U7 | - | N/A | None | |
NC | U8 | - | N/A | None | |
NC | U9 | - | N/A | None | |
NC | U10 | - | N/A | None | |
NC | U11 | - | N/A | None | |
NC | U12 | - | N/A | None | |
NC | V3 | - | N/A | None | |
NC | V4 | - | N/A | None | |
NC | V11 | - | N/A | None | |
NC | V12 | - | N/A | None | |
NC | W4 | - | N/A | None | |
NC | W11 | - | N/A | None | |
NC | W12 | - | N/A | None | |
NC | W13 | - | N/A | None |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
VCC | F9 | 1.2V Power | N/A | None | Core supply |
VCC | F10 | ||||
VCC | H10 | ||||
VCC | J14 | ||||
VCC | K6 | ||||
VCC | K8 | ||||
VCC | K12 | ||||
VCC | K14 | ||||
VCC | L6 | ||||
VCC | M10 | ||||
VCC | P10 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
VCCIO | F6 | 3.3V Power | N/A | None | Operating supply for I/Os |
VCCIO | F7 | ||||
VCCIO | F11 | ||||
VCCIO | F12 | ||||
VCCIO | F13 | ||||
VCCIO | F14 | ||||
VCCIO | G6 | ||||
VCCIO | G14 | ||||
VCCIO | H6 | ||||
VCCIO | H14 | ||||
VCCIO | J6 | ||||
VCCIO | L14 | ||||
VCCIO | M6 | ||||
VCCIO | M14 | ||||
VCCIO | N6 | ||||
VCCIO | N14 | ||||
VCCIO | P6 | ||||
VCCIO | P7 | ||||
VCCIO | P8 | ||||
VCCIO | P9 | ||||
VCCIO | P12 | ||||
VCCIO | P13 | ||||
VCCIO | P14 |
Terminal | Signal Type | Reset Pull State | Pull Type | Description | |
---|---|---|---|---|---|
Signal Name | 337 ZWT | ||||
VSS | A1 | Ground | N/A | None | Ground reference |
VSS | A2 | ||||
VSS | A18 | ||||
VSS | A19 | ||||
VSS | B1 | ||||
VSS | B19 | ||||
VSS | H8 | ||||
VSS | H9 | ||||
VSS | H11 | ||||
VSS | H12 | ||||
VSS | J8 | ||||
VSS | J9 | ||||
VSS | J10 | ||||
VSS | J11 | ||||
VSS | J12 | ||||
VSS | K9 | ||||
VSS | K10 | ||||
VSS | K11 | ||||
VSS | L8 | ||||
VSS | L9 | ||||
VSS | L10 | ||||
VSS | L11 | ||||
VSS | L12 | ||||
VSS | M8 | ||||
VSS | M9 | ||||
VSS | M11 | ||||
VSS | M12 | ||||
VSS | V1 | ||||
VSS | W1 | ||||
VSS | W2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply voltage range: | VCC(2) | -0.3 | 1.43 | V | |
VCCIO, VCCP(2) | -0.3 | 4.6 | V | ||
VCCAD | -0.3 | 6.25 | V | ||
Input voltage range: | All input pins, with exception of ADC pins | -0.3 | 4.6 | V | |
ADC input pins | -0.3 | 6.25 | V | ||
Input clamp current: | IIK (VI < 0 or VI > VCCIO) All pins, except AD1IN[23:0] or AD2IN[15:0] |
-20 | +20 | mA | |
IIK (VI < 0 or VI > VCCAD) AD1IN[23:0] or AD2IN[15:0] |
-10 | +10 | mA | ||
Total | -40 | +40 | mA | ||
Operating free-air temperature range, TA: | -40 | 105 | °C | ||
Operating junction temperature range, TJ: | -40 | 130 | °C | ||
Storage temperature range, Tstg | -65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge (ESD) performance: | Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) | ±2 | kV | |
Charged device model (CDM), per JESD22-C101(2) | All pins | ±250 | V |
NOMINAL CORE VOLTAGE (VCC) | JUNCTION TEMPERATURE (Tj) |
LIFETIME POH |
---|---|---|
1.2 | 105ºC | 100K |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Digital logic supply voltage (Core) | 1.14 | 1.2 | 1.32 | V | |
VCCPLL | PLL Supply Voltage | 1.14 | 1.2 | 1.32 | V | |
VCCIO | Digital logic supply voltage (I/O) | 3 | 3.3 | 3.6 | V | |
VCCAD | MibADC supply voltage | 3 | 5.25 | V | ||
VCCP | Flash pump supply voltage | 3 | 3.3 | 3.6 | V | |
VSS | Digital logic supply ground | 0 | V | |||
VSSAD | MibADC supply ground | -0.1 | 0.1 | V | ||
VADREFHI | A-to-D high-voltage reference source | VSSAD | VCCAD | V | ||
VADREFLO | A-to-D low-voltage reference source | VSSAD | VCCAD | V | ||
VSLEW | Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies | 1 | V/µs | |||
TA | Operating free-air temperature | -40 | 105 | °C | ||
TJ | Operating junction temperature(2) | -40 | 130 | °C |
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 200 MHz in pipelined mode with one address wait state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ICC | VCC digital supply current (operating mode) fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax |
fHCLK = 200MHz | 205(3) | 340(1) | mA | ||
VCC Digital supply current (LBIST/PBIST mode) |
LBIST/PBIST clock frequency = 100MHz |
265(3) | 455(2)(4) | mA | |||
ICCPLL | VCCPLL digital supply current (operating mode) | VCCPLL = VCCPLLmax | 10 | mA | |||
ICCIO | VCCIO Digital supply current (operating mode. | No DC load, VCCmax | 10 | mA | |||
ICCAD | VCCAD supply current (operating mode) | Single ADC operational, VCCADmax | 15 | mA | |||
Both ADCs operational, VCCADmax | 30 | ||||||
IADREFHI | ADREFHI supply current (operating mode) | Single ADC operational, ADREFHImax | 3 | mA | |||
Both ADCs operational, ADREFHImax | 6 | ||||||
ICCP | VCCP supply current | read from 1 bank and program another bank, VCCPmax | 55 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Vhys | Input hysteresis | All inputs | 180 | mV | |||
VIL | Low-level input voltage | All inputs | -0.3 | 0.8 | V | ||
VIH | High-level input voltage | All inputs | 2 | VCCIO + 0.3 | V | ||
VOL | Low-level output voltage | IOL = IOLmax | 0.2 VCCIO | V | |||
IOL = 50 µA, standard output mode | 0.2 | ||||||
IOL = 50 µA, low-EMI output mode (see Section 5.13) | 0.2 VCCIO | ||||||
VOH | High-level output voltage | IOH = IOHmax | 0.8 VCCIO | V | |||
IOH = 50 µA, standard output mode | VCCIO -0.3 | ||||||
IOH = 50 µA, low-EMI output mode (see Section 5.13) | 0.8 VCCIO | ||||||
IIK | Input clamp current (I/O pins)(2) | VI < VSSIO - 0.3 or VI > VCCIO + 0.3 | -3.5 | 3.5 | mA | ||
II | Input current (I/O pins) | IIH Pulldown 20µA | VI = VCCIO | 5 | 40 | µA | |
IIH Pulldown 100µA | VI = VCCIO | 40 | 195 | ||||
IIL Pullup 20µA | VI = VSS | -40 | -5 | ||||
IIL Pullup 100µA | VI = VSS | -195 | -40 | ||||
All other pins | No pullup or pulldown | -1 | 1 | ||||
CI | Input capacitance | 2 | pF | ||||
CO | Output capacitance | 3 | pF |
Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
LOW-LEVEL OUTPUT CURRENT, IOL for VI=VOLmax or HIGH-LEVEL OUTPUT CURRENT, IOH for VI=VOHmin |
SIGNALS |
---|---|
8 mA |
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3], TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15] ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B EMIF_ADDR[0:12], EMIF_BA[0:1], EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15], EMIF_nCAS, EMIF_nCS[0:4], EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE, EMIF_RNW MDCLK, MDIO, MII_RX_VCLKA4, MII_TX_VCLKA4, MII_TXD[0:3], MII_TXEN, RMII_REFCLK, RMII_TXD[0:1], RMII_TXEN USB1.PortPower, USB1.SPEED, USB1.SUSPEND, USB1.TXDAT, USB1.TXEN, USB1.TXSE0, USB2.PortPower, USB2.SPEED, USB2.SUSPEND, USB2.TXDAT, USB2.TXEN, USB2.TXSE0 ,USB_FUNC.GZO, USB_FUNC.PUENO, USB_FUNC.PUENON, USB_FUNC.SE0O, USB_FUNC.SUSPENDO, USB_FUNC.TXDO |
4 mA |
TEST, MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, ECAP2, ECAP3 nRST |
2 mA zero-dominant |
AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7], GIOB[0-7], LINRX, LINTX, MIBSPI1nCS[0], MIBSPI1nCS[1-3], MIBSPI1nENA, MIBSPI3nCS[0-3], MIBSPI3nENA, MIBSPI5nCS[0-3], MIBSPI5nENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15], N2HET2[16], N2HET2[18], SPI2nCS[0], SPI2nENA, SPI4nCS[0], SPI4nENA |
selectable 8 mA / 2 mA |
ECLK, SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8 mA for these signals. |
Signal | Control Bit | Address | 8 mA | 2 mA |
---|---|---|---|---|
ECLK | SYSPC10[0] | 0xFFFF FF78 | 0 | 1 |
SPI2CLK | SPI2PC9[9] | 0xFFF7 F668 | 0 | 1 |
SPI2SIMO | SPI2PC9[10] | 0xFFF7 F668 | 0 | 1 |
SPI2SOMI | SPI2PC9[11](1) | 0xFFF7 F668 | 0 | 1 |
Parameter | MIN | MAX | Unit | |
---|---|---|---|---|
tpw | Input minimum pulse width | tc(VCLK) + 10(2) | ns | |
tin_slew | Time for input signal to go from VIL to VIH or from VIH to VIL | 1 | ns |
Parameter | MIN | MAX | Unit | |||
---|---|---|---|---|---|---|
Rise time, tr | 8 mA low EMI pins (see Table 5-4) |
CL = 15 pF | 2.5 | ns | ||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Fall time, tf | CL = 15 pF | 2.5 | ns | |||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Rise time, tr | 4 mA low EMI pins (see Table 5-4) |
CL = 15 pF | 5.6 | ns | ||
CL = 50 pF | 10.4 | |||||
CL = 100 pF | 16.8 | |||||
CL = 150 pF | 23.2 | |||||
Fall time, tf | CL = 15 pF | 5.6 | ns | |||
CL= 50 pF | 10.4 | |||||
CL = 100 pF | 16.8 | |||||
CL = 150 pF | 23.2 | |||||
Rise time, tr | 2 mA-z low EMI pins (see Table 5-4) |
CL = 15 pF | 8 | ns | ||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Fall time, tf | CL = 15 pF | 8 | ns | |||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Rise time, tr | Selectable 8 mA / 2 mA-z pins (see Table 5-4) |
8 mA mode | CL = 15 pF | 2.5 | ns | |
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Fall time, tf | CL = 15 pF | 2.5 | ns | |||
CL = 50 pF | 4 | |||||
CL = 100 pF | 7.2 | |||||
CL = 150 pF | 12.5 | |||||
Rise time, tr | 2 mA-z mode | CL = 15 pF | 8 | ns | ||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 | |||||
Fall time, tf | CL = 15 pF | 8 | ns | |||
CL = 50 pF | 15 | |||||
CL = 100 pF | 23 | |||||
CL = 150 pF | 33 |
Parameter | MIN | MAX | UNIT | |
---|---|---|---|---|
td(parallel_out) | Delay between low to high, or high to low transition of general-purpose output signals that can be configured by an application in parallel, e.g. all signals in a GIOA port, or all N2HET1 signals, etc. | 6 | ns |
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an issue since the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode.
Module or Signal Name | Control Register to Enable Low-EMI Mode |
---|---|
Module: MibSPI1 | GPREG1.0 |
Module: SPI2 | GPREG1.1 |
Module: MibSPI3 | GPREG1.2 |
Reserved | GPREG1.3 |
Module: MibSPI5 | GPREG1.4 |
Reserved | GPREG1.5 |
Module: EMIF | GPREG1.6 |
Reserved | GPREG1.7 |
Signal: TMS | GPREG1.8 |
Signal: TDI | GPREG1.9 |
Signal: TDO | GPREG1.10 |
Signal: RTCK | GPREG1.11 |
Signal: TEST | GPREG1.12 |
Signal: nERROR | GPREG1.13 |
Signal: AD1EVT | GPREG1.14 |