6.2.1 Important Considerations

• The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
• The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter.

6.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

6.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000.

6.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.3.3.1 nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO	Parameter		MIN	MAX	Unit
	VCCPORL	VCC low supply level when nPORRST must be active during power-up		0.5	V
	VCCPORH	VCC high supply level when nPORRST must remain active during power-up and become active during power down	1.14		V
	VCCIOPORL	VCCIO / VCCP low supply level when nPORRST must be active during power-up		1.1	V
	VCCIOPORH	VCCIO / VCCP high supply level when nPORRST must remain active during power-up and become active during power down	3.0		V
	VIL(PORRST)	Low-level input voltage of nPORRST VCCIO > 2.5V		0.2 * VCCIO	V
		Low-level input voltage of nPORRST VCCIO < 2.5V		0.5	V
3	tsu(PORRST)	Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power-up	0		ms
6	th(PORRST)	Hold time, nPORRST active after VCC > VCCPORH	1		ms
7	tsu(PORRST)	Setup time, nPORRST active before VCC < VCCPORH during power down	2		µs
8	th(PORRST)	Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH	1		ms
9	th(PORRST)	Hold time, nPORRST active after VCC < VCCPORL	0		ms
	tf(nPORRST)	Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset.	475	2000	ns

Figure 6-1 nPORRST Timing Diagram

6.4.1 Causes of Warm Reset

6.4.2 nRST Timing Requirements

6.5.1 Summary of ARM Cortex-R4F CPU Features

The features of the ARM Cortex-R4F CPU include:

• An integer unit with integral Embedded ICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
• Floating Point Coprocessor
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Non-maskable interrupt.
• A Harvard Level one (L1) memory system with:
  • Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
  • ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
• Dual core logic for fault detection in safety-critical applications.
• An L2 memory interface:
  • Single 64-bit master AXI interface
  • 64-bit slave AXI interface to TCM RAM blocks
• A debug interface to a CoreSight Debug Access Port (DAP).
• Six Hardware Breakpoints
• Two Watchpoints
• A Performance Monitoring Unit (PMU).
• A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4F CPU, see www.arm.com.

6.5.2 ARM Cortex-R4F CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

• ECC On Tightly-Coupled Memory (TCM) Accesses
• Hardware Vectored Interrupt (VIC) Port
• Floating Point Coprocessor
• Memory Protection Unit (MPU)

6.5.3 Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock cycles as shown in Figure 6-3.

6.5.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety

This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in the figure below.

Figure 6-3 Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

6.5.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test as well as running few intervals at a time
• Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set)
• Complete isolation of the self-tested CPU core from rest of the system during the self-test run
• Ability to capture the Failure interval number
• Timeout counter for the CPU self-test run as a fail-safe feature

6.6.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

6.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in the figure below.

Figure 6-4 Recommended Crystal/Clock Connection

6.6.1.1.1 Timing Requirements for Main Oscillator

Table 6-9 Timing Requirements for Main Oscillator

Parameter		MIN	Type	MAX	Unit
tc(OSC)	Cycle time, OSCIN (when using a sine-wave input)	50		200	ns
tc(OSC_SQR)	Cycle time, OSCIN, (when input to the OSCIN is a square wave )	50		200	ns
tw(OSCIL)	Pulse duration, OSCIN low (when input to the OSCIN is a square wave)	15			ns
tw(OSCIH)	Pulse duration, OSCIN high (when input to the OSCIN is a square wave)	15			ns

6.6.1.2 Low Power Oscillator

The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

6.6.1.2.1 Features

The main features of the LPO are:

• Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module.
• Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5 of the Global Clock Module.
• Provides a comparison clock for the crystal oscillator failure detection circuit.

Figure 6-5 LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO) and provides two clock sources: one nominally 80KHz and one nominally 10MHz.

Table 6-10 LPO Specifications

Parameter		MIN	Typical	MAX	Unit
Clock Detection	oscillator fail frequency - lower threshold, using untrimmed LPO output	1.375	2.4	4.875	MHz
	oscillator fail frequency - higher threshold, using untrimmed LPO output	22	38.4	78	MHz
LPO - HF oscillator (fHFLPO)	untrimmed frequency	5.5	9	19.5	MHz
	trimmed frequency	8	9.6	11	MHz
	startup time from STANDBY (LPO BIAS_EN High for at least 900µs)			10	µs
	cold startup time			900	µs
LPO - LF oscillator	untrimmed frequency	36	85	180	kHz
	startup time from STANDBY (LPO BIAS_EN High for at least 900µs)			100	µs
	cold startup time			2000	µs

6.6.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled.
• Configurable frequency multipliers and dividers.
• Built-in PLL Slip monitoring circuit.
• Option to reset the device on a PLL slip detection.

6.6.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2.

Figure 6-6 PLLx Block Diagram

6.6.1.3.2 PLL Timing Specifications

Table 6-11 PLL Timing Specifications

PARAMETER		MIN	MAX	UNIT
fINTCLK	PLL1 Reference Clock frequency	1	f(OSC_SQR)	MHz
fpost_ODCLK	Post-ODCLK – PLL1 Post-divider input clock frequency		400	MHz
fVCOCLK	VCOCLK – PLL1 Output Divider (OD) input clock frequency	150	550	MHz
fINTCLK2	PLL2 Reference Clock frequency	1	f(OSC_SQR)	MHz
fpost_ODCLK2	Post-ODCLK – PLL2 Post-divider input clock frequency		400	MHz
fVCOCLK2	VCOCLK – PLL2 Output Divider (OD) input clock frequency	150	550	MHz

6.6.2 Clock Domains

6.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figures below.

Figure 6-7 Device Clock Domains

6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC

Some applications may need to use both the of Ethernet interfaces. The MII interface requires VCLKA4_DIVR_EMAC to be 25MHz and the RMII requires VCLKA4_DIVR_EMAC to be 50MHz.

These different frequencies are supported by adding special dedicated clock source selection options for the VCLKA4_DIVR_EMAC clock domain. This logic is shown in .

Figure 6-8 VCLKA4_DIVR Source Selection Options

The PLL2 post_ODCLK is brought out as a separate output from the PLL wrapper module. There are two additional dividers implemented at the device-level to divide this PLL2 post_ODCLK by 8 and by 16.

As shown in , the VCLKA4_SRC configured through the system module VCLKACON1 control register is used to determine the clock source for the VCLKA4_S and VCLKA4_DIVR. An additional multiplexor is implemented to select between the VCLKA4_DIVR and the two additional clock sources – PLL2 post_ODCLK/8 and post_ODCLK/16.

The selection is done as shown in the following table.

Table 6-14 VCLKA4_DIVR_EMAC Clock Source Selection

VCLKA4_SRC from VCLKACON1[19–16]	Clock Source for VCLKA4_DIVR_EMAC
0x0	OSCIN / VCLKA4R
0x1	PLL1CLK / VCLKA4R
0x2	Reserved
0x3	EXTCLKIN1 / VCLKA4R
0x4	LF LPO / VCLKA4R
0x5	HF LPO / VCLKA4R
0x6	PLL2CLK / VCLKA4R
0x7	EXTCLKIN2 / VCLKA4R

6.6.3 Clock Test Mode

The platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module.

6.7.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 6-10.

Figure 6-9 LPO and Clock Detection, Untrimmed HFLPO

6.7.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

6.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0.

Table 6-20 Glitch Filter Timing Specifications

6.9.1 Memory Map Diagram

The figure below shows the device memory map.

Figure 6-10 Memory Map

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.

6.9.2 Memory Map Table

6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s program status register (CPSR).

6.9.4 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module.

6.9.5 Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned OFF.

6.9.6 Parameter Overlay Module (POM) Considerations

• The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of the memory overlay are configurable through the POM control registers. Care must be taken to ensure that the overlay is mapped on to available memory.
• ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC errors will be generated.
• POM overlay must not be enabled when the flash and internal RAM memories are swapped through the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
• When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when another master accesses the TCM flash. This results in a system hang.
  • The POM implements a timeout feature to detect this exact scenario. The timeout needs to be enabled whenever POM overlay is enabled.
  • The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control register (POMGLBCTRL, address = 0xFFA04000).
  • In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO) flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a data fetch.
  • The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If so, then the application can assume that the timeout is caused by a bus contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to a timeout from the POM.

6.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

6.10.2 Main Features of Flash Module

• Support for multiple flash banks for program and/or data storage
• Simultaneous read access on a bank while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
  • Error address is captured for host system debugging
• Support for a rich set of diagnostic features

6.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1.

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.

6.10.5 Program Flash

6.10.6 Data Flash

6.11.1 Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

• Acts as slave to the BTCM interface of the Cortex-R4F CPU
• Supports the internal ECC scheme of the CPU by providing 64-bit data and 8-bit ECC code
• Monitors CPU Event Bus and generates single or multibit error interrupts
• Stores addresses for single and multibit errors
• Supports RAM trace module
• Provides CPU address bus integrity checking by supporting parity checking on the address bus
• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
• Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks
• Supports auto-initialization of the RAM banks along with the ECC bits

6.11.2 TCRAM ECC Support

The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also stores the contents of the CPU ECC port in the ECC RAM when the CPU does a write to the RAM. The TCRAM interface monitors the CPU event bus and provides registers for indicating single/multibit errors and also for identifying the address that caused the single or multibit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information see RM46x Technical Reference Manual (SPNU514).

6.13.1 On-Chip SRAM Self-Test Using PBIST

6.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers see RM46x Technical Reference Manual (SPNU514).

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-27.

6.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices. The EMIF features includes support for:

• 3 addressable chip select for asynchronous memories of up to 32KB each
• 1 addressable chip select space for SDRAMs up to 128MB
• 8 or 16-bit data bus width
• Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
• Select strobe mode
• Extended Wait mode
• Data bus parking

6.14.2 Electrical and Timing Specifications

6.14.2.1 Asynchronous RAM

Figure 6-12 Asynchronous Memory Read Timing

Figure 6-13 EMIFnWAIT Read Timing Requirements

Figure 6-14 Asynchronous Memory Write Timing

Figure 6-15 EMIFnWAIT Write Timing Requirements

Table 6-28 EMIF Asynchronous Memory Timing Requirements⁽¹⁾

NO.			Value			Unit
			MIN	NOM	MAX
Reads and Writes
	E	EMIF clock period	9			ns
2	tw(EM_WAIT)	Pulse duration, EMIF_nWAIT assertion and deassertion	2E			ns
Reads
12	tsu(EMDV-EMOEH)	Setup time, EMIF_DATA[15:0] valid before EMIFnOE high	9			ns
13	th(EMOEH-EMDIV)	Hold time, EMIF_DATA[15:0] valid after EMIF_nOE high	0			ns
14	tsu(EMOEL-EMWAIT)	Setup Time, EMIF_nWAIT asserted before end of Strobe Phase(2)	4E+9			ns
Writes
28	tsu(EMWEL-EMWAIT)	Setup Time, EMIF_nWAIT asserted before end of Strobe Phase(2)	4E+14			ns

(1) E = EMIF_CLK period in ns.

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended wait states. Figure 6-13 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 6-29 EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)

NO	PARAMETER		Value			UNIT
			MIN	NOM	MAX
Reads and Writes
1	td(TURNAROUND)	Turnaround time	(TA)*E - 4	(TA)*E	(TA)*E + 3	ns
Reads
3	tc(EMRCYCLE)	EMIF read cycle time (EW = 0)	(RS+RST+RH)*E -3	(RS+RST+RH)*E	(RS+RST+RH)*E + 3	ns
		EMIF read cycle time (EW = 1)	(RS+RST+RH+(EWC*16))*E -3	(RS+RST+RH+(EWC*16))*E	(RS+RST+RH+(EWC*16))*E + 3	ns
4	tsu(EMCEL-EMOEL)	Output setup time, EMIF_nCS[4:2] low to EMIF_nOE low (SS = 0)	(RS)*E-6	(RS)*E	(RS)*E+3	ns
		Output setup time, EMIF_nCS[4:2] low to EMIF_nOE low (SS = 1)	-6	0	+3	ns
5	th(EMOEH-EMCEH)	Output hold time, EMIF_nOE high to EMIF_nCS[4:2] high (SS = 0)	(RH)*E -3	(RH)*E	(RH)*E + 5	ns
		Output hold time, EMIF_nOE high to EMIF_nCS[4:2] high (SS = 1)	-3	0	+5	ns
6	tsu(EMBAV-EMOEL)	Output setup time, EMIF_BA[1:0] valid to EMIF_nOE low	(RS)*E-6	(RS)*E	(RS)*E+3	ns
7	th(EMOEH-EMBAIV)	Output hold time, EMIF_nOE high to EMIF_BA[1:0] invalid	(RH)*E-3	(RH)*E	(RH)*E+5	ns
8	tsu(EMAV-EMOEL)	Output setup time, EMIF_ADDR[12:0] valid to EMIFnOE low	(RS)*E-6	(RS)*E	(RS)*E+3	ns
9	th(EMOEH-EMAIV)	Output hold time, EMIF_nOE high to EMIF_ADDR[12:0] invalid	(RH)*E-3	(RH)*E	(RH)*E+5	ns
10	tw(EMOEL)	EMIF_nOE active low width (EW = 0)	(RST)*E-3	(RST)*E	(RST)*E+3	ns
		EMIF_nOE active low width (EW = 1)	(RST+(EWC*16)) *E-3	(RST+(EWC*16))*E	(RST+(EWC*16)) *E+3	ns
11	td(EMWAITH-EMOEH)	Delay time from EMIF_nWAIT deasserted to EMIF_nOE high	3E+9	4E	4E+20	ns
29	tsu(EMDQMV-EMOEL)	Output setup time, EMIF_nDQM[1:0] valid to EMIF_nOE low	(RS)*E-6	(RS)*E	(RS)*E+3	ns
30	th(EMOEH-EMDQMIV)	Output hold time, EMIF_nOE high to EMIF_nDQM[1:0] invalid	(RH)*E-3	(RH)*E	(RH)*E+5	ns
Writes
15	tc(EMWCYCLE)	EMIF write cycle time (EW = 0)	(WS+WST+WH)* E-3	(WS+WST+WH)*E	(WS+WST+WH)* E+3	ns
		EMIF write cycle time (EW = 1)	(WS+WST+WH+( EWC*16))*E -3	(WS+WST+WH+(E WC*16))*E	(WS+WST+WH+( EWC*16))*E + 3	ns
16	tsu(EMCEL-EMWEL)	Output setup time, EMIF_nCS[4:2] low to EMIF_nWE low (SS = 0)	(WS)*E -3	(WS)*E	(WS)*E + 3	ns
		Output setup time, EMIF_nCS[4:2] low to EMIF_nWE low (SS = 1)	-3	0	+3	ns
17	th(EMWEH-EMCEH)	Output hold time, EMIF_nWE high to EMIF_nCS[4:2] high (SS = 0)	(WH)*E-3	(WH)*E	(WH)*E+3	ns
		Output hold time, EMIF_nWE high to EMIF_CS[4:2] high (SS = 1)	-3	0	+3	ns
18	tsu(EMDQMV-EMWEL)	Output setup time, EMIF_BA[1:0] valid to EMIF_nWE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
19	th(EMWEH-EMDQMIV)	Output hold time, EMIF_nWE high to EMIF_BA[1:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
20	tsu(EMBAV-EMWEL)	Output setup time, EMIF_BA[1:0] valid to EMIF_nWE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
21	th(EMWEH-EMBAIV)	Output hold time, EMIF_nWE high to EMIF_BA[1:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
22	tsu(EMAV-EMWEL)	Output setup time, EMIF_ADDR[12:0] valid to EMIF_nWE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
23	th(EMWEH-EMAIV)	Output hold time, EMIF_nWE high to EMIF_ADDR[12:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
24	tw(EMWEL)	EMIF_nWE active low width (EW = 0)	(WST)*E-3	(WST)*E	(WST)*E+3	ns
		EMIF_nWE active low width (EW = 1)	(WST+(EWC*16)) *E-3	(WST+(EWC*16))*E	(WST+(EWC*16)) *E+3	ns
25	td(EMWAITH-EMWEH)	Delay time from EMIF_nWAIT deasserted to EMIF_nWE high	3E+11	4E	4E+24	ns
26	tsu(EMDV-EMWEL)	Output setup time, EMIF_DATA[15:0] valid to EMIF_nWE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
27	th(EMWEH-EMDIV)	Output hold time, EMIF_nWE high to EMIF_DATA[15:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
31	tsu(EMDQMV-EMWEL)	Output setup time, EMIF_nDQM[1:0] valid to EMIF_nWE low	(WH)*E-3	(WH)*E	(WH)*E+3	ns
32	th(EMWEH-EMDQMIV)	Output hold time, EMIF_nWE high to EMIF_nDQM[1:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns

(1) TA = Turnaround, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1], WH[8–1], and MEWC[1–256]. See the RM46x Technical Reference Manual (SPNU514) for more information.

(2) E = EMIF_CLK period in ns.

(3) EWC = external wait cycles determined by EMIF_nWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the RM46x Technical Reference Manual (SPNU514) for more information.

6.14.2.2 Synchronous Timing

Figure 6-16 Basic SDRAM Read Operation

Figure 6-17 Basic SDRAM Write Operation

Table 6-30 EMIF Synchronous Memory Timing Requirements

NO.	Parameter		MIN	MAX	Unit
19	tsu(EMIFDV-EM_CLKH)	Input setup time, read data valid on EMIF_DATA[15:0] before EMIF_CLK rising	2		ns
20	th(CLKH-DIV)	Input hold time, read data valid on EMIF_DATA[15:0] after EMIF_CLK rising	2		ns

Table 6-31 EMIF Synchronous Memory Switching Characteristics

NO.	Parameter		MIN	MAX	Unit
1	tc(CLK)	Cycle time, EMIF clock EMIF_CLK	18		ns
2	tw(CLK)	Pulse width, EMIF clock EMIF_CLK high or low	5		ns
3	td(CLKH-CSV)	Delay time, EMIF_CLK rising to EMIF_nCS[0] valid		13	ns
4	toh(CLKH-CSIV)	Output hold time, EMIF_CLK rising to EMIF_nCS[0] invalid	1		ns
5	td(CLKH-DQMV)	Delay time, EMIF_CLK rising to EMIF_nDQM[1:0] valid		13	ns
6	toh(CLKH-DQMIV)	Output hold time, EMIF_CLK rising to EMIF_nDQM[1:0] invalid	1		ns
7	td(CLKH-AV)	Delay time, EMIF_CLK rising to EMIF_ADDR[12:0] and EMIFBA[1:0] valid		13	ns
8	toh(CLKH-AIV)	Output hold time, EMIF_CLK rising to EMIF_ADDR[12:0] and EMIF_BA[1:0] invalid	1		ns
9	td(CLKH-DV)	Delay time, EMIF_CLK rising to EMIF_DATA[15:0] valid		13	ns
10	toh(CLKH-DIV)	Output hold time, EMIF_CLK rising to EMIF_DATA[15:0] invalid	1		ns
11	td(CLKH-RASV)	Delay time, EMIF_CLK rising to EMIF_nRAS valid		13	ns
12	toh(CLKH-RASIV)	Output hold time, EMIF_CLK rising to EMIF_nRAS invalid	1		ns
13	td(CLKH-CASV)	Delay time, EMIF_CLK rising to EMIF_nCAS valid		13	ns
14	toh(CLKH-CASIV)	Output hold time, EMIF_CLK rising to EMIF_nCAS invalid	1		ns
15	td(CLKH-WEV)	Delay time, EMIF_CLK rising to EMIF_nWE valid		13	ns
16	toh(CLKH-WEIV)	Output hold time, EMIF_CLK rising to EMIF_nWE invalid	1		ns
17	tdis(CLKH-DHZ)	Delay time, EMIF_CLK rising to EMIF_DATA[15:0] tri-stated		7	ns
18	tena(CLKH-DLZ)	Output hold time, EMIF_CLK rising to EMIF_DATA[15:0] driving	1		ns

6.15.1 VIM Features

The VIM module has the following features:

• Supports 128 interrupt channels.
  • Provides programmable priority and enable for interrupt request lines.
• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
• Provides two software dispatch mechanisms when the CPU VIC port is not used.
  • Index interrupt
  • Register vectored interrupt
• Parity protected vector interrupt table against soft errors.

6.15.2 Interrupt Request Assignments

6.16.1 DMA Features

• CPU independent data transfer
• One 64-bit master port that interfaces to the TMS570 Memory System.
• FIFO buffer(4 entries deep and each 64bit wide)
• Channel control information is stored in RAM protected by parity
• 16 channels with individual enable
• Channel chaining capability
• 32 peripheral DMA requests
• Hardware and Software DMA requests
• 8, 16, 32 or 64-bit transactions supported
• Multiple addressing modes for source/destination (fixed, increment, offset)
• Auto-initiation
• Power-management mode
• Memory Protection with four configurable memory regions

6.16.2 Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in Table 6-33. The application must ensure that only one of these DMA request sources is enabled at any time.

6.17.1 Features

The RTI module has the following features:

• Two independent 64 bit counter blocks
• Four configurable compares for generating operating system ticks or DMA requests. Each event can be driven by either counter block 0 or counter block 1.
• Fast enabling/disabling of events
• Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.17.2 Block Diagrams

Figure 6-18 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as time base inputs for the counter block 0.

Figure 6-18 Counter Block Diagram

Figure 6-19 Compare Block Diagram

6.17.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources refer to Table 6-8 and Table 6-13.

6.17.4 Network Time Synchronization Inputs

The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as shown below.

6.18.1 Features

The features of the Error Signaling Module are:

• 128 interrupt/error channels are supported, divided into 3 different groups
  • 64 channels with maskable interrupt and configurable error pin behavior
  • 32 error channels with non-maskable interrupt and predefined error pin behavior
  • 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability

6.18.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-36 shows the channel assignment for each group.

Table 6-37 Reset/Abort/Error Sources

6.21.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains.

Figure 6-20 Debug Subsystem Block Diagram

6.21.2 Debug Components Memory Map

6.21.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code.

6.21.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

6.21.5 JTAG Scan Interface Timings

Figure 6-21 JTAG Timing

6.21.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the device’s memory content by allowing users to secure the device after programming.

Figure 6-22 AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state.

6.21.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

Figure 6-23 Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.