SPNS176C April   2012  – June 2015 RM48L530 , RM48L730

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.1.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.3.1.3  General-Purpose Input/Output (GPIO)
        4. 4.3.1.4  Controller Area Network Controllers (DCANs)
        5. 4.3.1.5  Local Interconnect Network Interface Module (LIN)
        6. 4.3.1.6  Standard Serial Communication Interface (SCI)
        7. 4.3.1.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.3.1.8  Standard Serial Peripheral Interface (SPI)
        9. 4.3.1.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.3.1.10 USB Host and Device Port Controller Interface
        11. 4.3.1.11 System Module Interface
        12. 4.3.1.12 Clock Inputs and Outputs
        13. 4.3.1.13 Test and Debug Modules Interface
        14. 4.3.1.14 Flash Supply and Test Pads
        15. 4.3.1.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.3.1.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.3.1.17 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.2.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.3.2.3  General-Purpose Input/Output (GPIO)
        4. 4.3.2.4  Controller Area Network Controllers (DCANs)
        5. 4.3.2.5  Local Interconnect Network Interface Module (LIN)
        6. 4.3.2.6  Standard Serial Communication Interface (SCI)
        7. 4.3.2.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.3.2.8  Standard Serial Peripheral Interface (SPI)
        9. 4.3.2.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.3.2.10 USB Host and Device Port Controller Interface
        11. 4.3.2.11 External Memory Interface (EMIF)
        12. 4.3.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        13. 4.3.2.13 RAM Trace Port (RTP)
        14. 4.3.2.14 Data Modification Module (DMM)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2-V Nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3-V Nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Input/Output Electrical Characteristics
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator (LPO)
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Peripheral Legend
    2. 7.2  Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3  General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4  Enhanced Next Generation High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HTU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5  Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6  Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7  Serial Communication Interface (SCI)
      1. 7.7.1 Features
    8. 7.8  Inter-Integrated Circuit (I2C)
      1. 7.8.1 Features
      2. 7.8.2 I2C I/O Timing Specifications
    9. 7.9  Multibuffered / Standard Serial Peripheral Interface
      1. 7.9.1 Features
      2. 7.9.2 MibSPI Transmit and Receive RAM Organization
      3. 7.9.3 MibSPI Transmit Trigger Events
        1. 7.9.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.9.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.9.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.9.5 SPI Slave Mode I/O Timings
    10. 7.10 Universal Serial Bus (USB) Host and Device Controllers
      1. 7.10.1 Features
      2. 7.10.2 Electrical and Timing Specifications
  8. 8Device and Documentation Support
    1. 8.1  Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2  Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3  Related Links
    4. 8.4  Community Resources
    5. 8.5  Trademarks
    6. 8.6  Electrostatic Discharge Caution
    7. 8.7  Glossary
    8. 8.8  Device Identification Code Register
    9. 8.9  Die Identification Registers
    10. 8.10 Module Certifications
      1. 8.10.1 DCAN Certification
      2. 8.10.2 LIN Certification
        1. 8.10.2.1 LIN Master Mode
        2. 8.10.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.10.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGE|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Peripheral Information and Electrical Specifications

7.1 Peripheral Legend

Table 7-1 Peripheral Legend

ABBREVIATION FULL NAME
MibADC Analog-to-Digital Converter
CCM-R4F CPU Compare Module - Cortex-R4F
CRC Cyclic Redundancy Checker
DCAN Controller Area Network
DCC Dual Clock Comparator
DMA Direct Memory Access
DMM Data Modification Module
EMIF External Memory Interface
ESM Error Signaling Module
ETM-R4F Embedded Trace Macrocell - Cortex-R4F
GPIO General-Purpose Input/Output
HTU High-End Timer Transfer Unit
I2C Inter-Integrated Circuit
LIN Local Interconnect Network
MibSPI Multibuffered Serial Peripheral Interface
N2HET Platform Next Generation High-End Timer
POM Parameter Overlay Module
RTI Real-Time Interrupt Module
RTP RAM Trace Port
SPI Serial Peripheral Interface
USB Universal Serial Bus
VIM Vectored Interrupt Manager

7.2 Multibuffered 12-Bit Analog-to-Digital Converter

The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted.

Table 7-2 MibADC Overview

DESCRIPTION VALUE
Resolution 12 bits
Monotonic Assured
Output conversion code 00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI]

7.2.1 Features

  • 10-/12-bit resolution
  • ADREFHI and ADREFLO pins (high and low reference voltages)
  • Total Sample/Hold/Convert time: 600 ns Typical Minimum at 30 MHz ADCLK
  • One memory region per conversion group is available (event, group 1, group 2)
  • Allocation of channels to conversion groups is completely programmable
  • Memory regions are serviced either by interrupt or by DMA
  • Programmable interrupt threshold counter is available for each group
  • Programmable magnitude threshold interrupt for each group for any one channel
  • Option to read either 8-, 10-, or 12-bit values from memory regions
  • Single or continuous conversion modes
  • Embedded self-test
  • Embedded calibration logic
  • Enhanced power-down mode
    • Optional feature to automatically power down ADC core when no conversion is in progress
  • External event pin (ADEVT) programmable as general-purpose I/O

7.2.2 Event Trigger Options

The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these three groups can be configured to be hardware event-triggered. In that case, the application can select from among eight event sources to be the trigger for a group's conversions.

7.2.2.1 Default MIBADC1 Event Trigger Hookup

Table 7-3 MIBADC1 Event Trigger Hookup

Event # Source Select Bits For G1, G2 Or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])		 Trigger
1 000 ADEVT
2 001 N2HET1[8]
3 010 N2HET1[10]
4 011 RTI compare 0 interrupt
5 100 N2HET1[12]
6 101 N2HET1[14]
7 110 GIOB[0]
8 111 GIOB[1]

NOTE

For ADEVT, N2HET1, and GIOB trigger sources, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (via the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the ADEVT, N2HET1[x], or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.2.2.2 Alternate MIBADC1 Event Trigger Hookup

Table 7-4 Alternate MIBADC1 Event Trigger Hookup

EVENT # SOURCE SELECT BITS FOR G1, G2 OR EVENT
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])		 TRIGGER
1 000 ADEVT
2 001 N2HET2[5]
3 010 N2HET1[27]
4 011 RTI compare 0 interrupt
5 100 N2HET1[17]
6 101 N2HET1[19]
7 110 N2HET1[11]
8 111 N2HET2[13]

The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger hook-up is done by multiplexing control module register 30 bits 0 and 1.

If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.

If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.

NOTE

For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring ADEVT as an output function on to the pad (via the mux control), or by driving the ADEVT signal from an external trigger source as input. If the mux control module is used to select different functionality instead of the ADEVT signal, then care must be taken to disable ADEVT from triggering conversions; there is no multiplexing on the input connection.

NOTE

For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made from the input side of the output buffer (at the N2HETx module boundary). This way, a trigger condition can be generated even if the N2HETx signal is not selected to be output on the pad.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.2.2.3 Default MIBADC2 Event Trigger Hookup

Table 7-5 MIBADC2 Event Trigger Hookup

EVENT # SOURCE SELECT BITS FOR G1, G2 OR EVENT
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])		 TRIGGER
1 000 AD2EVT
2 001 N2HET1[8]
3 010 N2HET1[10]
4 011 RTI compare 0
5 100 N2HET1[12]
6 101 N2HET1[14]
7 110 GIOB[0]
8 111 GIOB[1]

NOTE

For AD2EVT, N2HET1 and GIOB trigger sources, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (via the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.2.2.4 Alternate MIBADC2 Event Trigger Hookup

Table 7-6 Alternate MIBADC2 Event Trigger Hookup

EVENT # SOURCE SELECT BITS FOR G1, G2 OR EVENT
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])		 TRIGGER
1 000 AD2EVT
2 001 N2HET2[5]
3 010 N2HET1[27]
4 011 RTI compare 0
5 100 N2HET1[17]
6 101 N2HET1[19]
7 110 N2HET1[11]
8 111 N2HET2[13]

The selection between the default MIBADC2 event trigger hook-up versus the alternate event trigger hook-up is done by multiplexing control module register 30 bits 0 and 1.

If 30[0] = 1, then the default MibADC2 event trigger hook-up is used.

If 30[0] = 0 and 30[1] = 1, then the alternate MibADC2 event trigger hook-up is used.

NOTE

For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring AD2EVT as an output function on to the pad (via the mux control), or by driving the AD2EVT signal from an external trigger source as input. If the mux control module is used to select different functionality instead of the AD2EVT signal, then care must be taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input connections.

NOTE

For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made from the input side of the output buffer (at the N2HETx module boundary). This way, a trigger condition can be generated even if the N2HETx signal is not selected to be output on the pad.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.2.3 ADC Electrical and Timing Specifications

Table 7-7 MibADC Recommended Operating Conditions

PARAMETER MIN MAX UNIT
ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD(1) V
ADREFLO A-to-D low-voltage reference source VSSAD(1) ADREFHI V
VAI Analog input voltage ADREFLO ADREFHI V
IAIK Analog input clamp current(2)
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)		 –2 2 mA
(1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 7-8 MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions

PARAMETER DESCRIPTION/CONDITIONS MIN MAX UNIT
Rmux Analog input mux on-resistance See Figure 7-1 250 Ω
Rsamp ADC sample switch on-resistance See Figure 7-1 250 Ω
Cmux Input mux capacitance See Figure 7-1 16 pF
Csamp ADC sample capacitance See Figure 7-1 13 pF
IAIL Analog off-state input leakage current VCCAD = 3.6 V
maximum		 VSSAD ≤ VIN < VSSAD + 100 mV –300 200 nA
VSSAD + 100 mV ≤ VIN ≤ VCCAD - 200 mV –200 200
VCCAD - 200 mV < VIN ≤ VCCAD –200 500
IAIL Analog off-state input leakage current VCCAD = 5.5 V
maximum		 VSSAD ≤ VIN < VSSAD + 300 mV –1000 250 nA
VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV –250 250
VCCAD - 300 mV < VIN ≤ VCCAD –250 1000
IAOSB1(1) ADC1 Analog on-state input bias current VCCAD = 3.6 V
maximum		 VSSAD ≤ VIN < VSSAD + 100 mV –8 2 µA
VSSAD + 100 mV < VIN < VCCAD - 200 mV –4 2
VCCAD - 200 mV < VIN < VCCAD –4 12
IAOSB2(1) ADC2 Analog on-state input bias current VCCAD = 3.6 V
maximum		 VSSAD ≤ VIN < VSSAD + 100 mV –7 2 µA
VSSAD + 100 mV ≤ VIN ≤ VCCAD - 200 mV –4 2
VCCAD - 200 mV < VIN ≤ VCCAD –4 10
IAOSB1(1) ADC1 Analog on-state input bias current VCCAD = 5.5 V
maximum		 VSSAD ≤ VIN < VSSAD + 300  mV –10 3 µA
VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV –5 3
VCCAD - 300 mV < VIN ≤ VCCAD –5 14
IAOSB2(1) ADC2 Analog on-state input bias current VCCAD = 5.5 V
maximum		 VSSAD ≤ VIN < VSSAD + 300 mV –8 3 µA
VSSAD + 300 mV ≤ VIN ≤ VCCAD - 300 mV –5 3
VCCAD - 300 mV < VIN ≤ VCCAD –5 12
IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA
ICCAD Static supply current Normal operating mode 15 mA
ADC core in power down mode 5 µA
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSL1 + IAOSL2
RM48L930 RM48L730 RM48L530 mibadc_circuit_pns160.gifFigure 7-1 MibADC Input Equivalent Circuit

Table 7-9 MibADC Timing Specifications

PARAMETER MIN NOM MAX UNIT
tc(ADCLK)(2) Cycle time, MibADC clock 0.033 µs
td(SH)(3) Delay time, sample and hold time 0.2 µs
td(PU-ADV) Delay time from ADC power on until first input can be sampled 1 µs
12-BIT MODE
td(c) Delay time, conversion time 0.4 µs
td(SHC)(1) Delay time, total sample/hold and conversion time 0.6 µs
10-BIT MODE
td(c) Delay time, conversion time 0.33 µs
td(SHC)(1) Delay time, total sample/hold and conversion time 0.53 µs
(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for example, the prescale settings.
(2) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits 4:0.
(3) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as well as the internal impedance of the ADC.

Table 7-10 MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions

PARAMETER DESCRIPTION/CONDITIONS MIN NOM MAX UNIT
CR Conversion range over which specified accuracy is maintained ADREFHI - ADREFLO 3 5.5 V
ZSET Zero Scale Offset Difference between the first ideal transition (from code 000h to 001h) and the actual transition 10-bit mode 1 LSB(1)
12-bit mode 2 LSB(2)
FSET Full Scale Offset Difference between the range of the measured code transitions (from first to last) and the range of the ideal code transitions 10-bit mode 2 LSB
12-bit mode 3 LSB
EDNL Differential nonlinearity error Difference between the actual step width and the ideal value. (see Figure 7-2) 10-bit mode ± 1.5 LSB
12-bit mode ± 2 LSB
EINL Integral nonlinearity error Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. 10-bit mode ± 2 LSB
12-bit mode ± 2 LSB
ETOT Total unadjusted error Maximum value of the difference between an analog value and the ideal midstep value. 10-bit mode ± 2 LSB
12-bit mode ± 4 LSB
(1) 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode
(2) 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode

7.2.4 Performance (Accuracy) Specifications

7.2.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 7-2 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB.

RM48L930 RM48L730 RM48L530 dnl_error_pns160.gifFigure 7-2 Differential Nonlinearity (DNL) Error

The integral nonlinearity error shown in Figure 7-3 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line.

RM48L930 RM48L730 RM48L530 inl_error_pns160.gifFigure 7-3 Integral Nonlinearity (INL) Error

7.2.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 7-4 is the maximum value of the difference between an analog value and the ideal midstep value.

RM48L930 RM48L730 RM48L530 total_error_pns160.gifFigure 7-4 Absolute Accuracy (Total) Error

7.3 General-Purpose Input/Output

The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable. Both GIOA and GIOB support external interrupt capability.

7.3.1 Features

The GPIO module has the following features:

  • Each I/O pin can be configured as:
    • Input
    • Output
    • Open Drain
  • The interrupts have the following characteristics:
    • Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
    • Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
    • Individual interrupt flags (set in GIOFLG register)
    • Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers, respectively
    • Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
  • Internal pullup or pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see Section 5.11 and Section 5.12

7.4 Enhanced Next Generation High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.

7.4.1 Features

The N2HET module has the following features:

  • Programmable timer for input and output timing functions
  • Reduced instruction set (30 instructions) for dedicated time and angle functions
  • 160 words of instruction RAM protected by parity
  • User-defined number of 25-bit virtual counters for timer, event counters and angle counters
  • 7-bit hardware counters for some pins allow up to 32-bit resolution in conjunction with the 25-bit virtual counters
  • Up to 32 pins usable for input signal measurements or output signal generation
  • Programmable suppression filter for each input pin with adjustable limiting frequency
  • Low CPU overhead and interrupt load
  • Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU) or DMA
  • Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

7.4.2 N2HET RAM Organization

The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one RAM address may be written while another address is read. The RAM words are 96 bits wide, which are split into three 32-bit fields (program, control, and data).

7.4.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

RM48L930 RM48L730 RM48L530 nhet_input_timings_pns160.gifFigure 7-5 N2HET Input Capture Timings

Table 7-11 Input Timing Requirements for the N2HET Input Capture Functionality

NO. MIN(1)(2) MAX(1)(2) UNIT
1 Input signal period, PCNT or WCAP for rising edge to rising edge 2 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
2 Input signal period, PCNT or WCAP for falling edge to falling edge 2 (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
3 Input signal high phase, PCNT or WCAP for rising edge to falling edge (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
4 Input signal low phase, PCNT or WCAP for falling edge to rising edge (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR).

Both N2HET1 and N2HET2 have channels that are enhanced to be able to capture inputs with smaller pulse widths than that specified in Table 7-11. See Table 7-13 for a list of which pins support small pulse capture.

The input capture capability for these channels is specified in Table 7-12.

Table 7-12 Input Timing Requirements for N2HET Channels with Enhanced Pulse Capture

NO. MIN MAX UNIT
1 Input signal period, PCNT or WCAP for rising edge to rising edge (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
2 Input signal period, PCNT or WCAP for falling edge to falling edge (hr) (lr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
3 Input signal high phase, PCNT or WCAP for rising edge to falling edge 2 (hr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns
4 Input signal low phase, PCNT or WCAP for falling edge to rising edge 2 (hr) tc(VCLK2) + 2 225 (hr) (lr) tc(VCLK2) - 2 ns

Table 7-13 Input Capture Pin Capability

CHANNEL SUPPORTS 32-BIT CAPTURE ENHANCED PULSE CAPTURE
N2HET1[00] Yes No
N2HET1[01] Yes No
N2HET1[02] Yes No
N2HET1[03] Yes No
N2HET1[04] Yes No
N2HET1[05] Yes No
N2HET1[06] Yes No
N2HET1[07] Yes No
N2HET1[08] Yes No
N2HET1[09] Yes No
N2HET1[10] Yes No
N2HET1[11] Yes No
N2HET1[12] Yes No
N2HET1[13] Yes No
N2HET1[14] Yes No
N2HET1[15] Yes Yes
N2HET1[16] Yes No
N2HET1[17] Yes No
N2HET1[18] Yes No
N2HET1[19] Yes No
N2HET1[20] Yes Yes
N2HET1[21] Yes No
N2HET1[22] Yes No
N2HET1[23] Yes No
N2HET1[24] Yes No
N2HET1[25] Yes No
N2HET1[26] Yes No
N2HET1[27] Yes No
N2HET1[28] Yes No
N2HET1[29] Yes No
N2HET1[30] Yes No
N2HET1[31] Yes Yes
N2HET2[00] Yes No
N2HET2[01] No No
N2HET2[02] No No
N2HET2[03] No No
N2HET2[04] Yes No
N2HET2[05] No No
N2HET2[06] Yes No
N2HET2[07] No No
N2HET2[08] No No
N2HET2[09] No No
N2HET2[10] No No
N2HET2[11] No No
N2HET2[12] Yes Yes
N2HET2[13] No No
N2HET2[14] Yes Yes
N2HET2[15] No No
N2HET2[16] Yes Yes
N2HET2[18] No No

7.4.4 N2HET1-N2HET2 Interconnections

In some applications the N2HET resolutions must be synchronized. Some other applications require a single time base to be used for all PWM outputs and input timing captures.

The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to the loop resolution signal sent by the master. The slave does not require this signal after it receives the first synchronization signal. However, anytime the slave receives the resynchronization signal from the master, the slave must synchronize itself again..

RM48L930 RM48L730 RM48L530 nhet_interconnect_pns160.gifFigure 7-6 N2HET1 – N2HET2 Synchronization Hookup

7.4.5 N2HET Checking

7.4.5.1 Internal Monitoring

To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be used to monitor each other’s signals as shown in Figure 7-7. The direction of the monitoring is controlled by the I/O multiplexing control module.

RM48L930 RM48L730 RM48L530 nhet_monitoring_pns160.gifFigure 7-7 N2HET Monitoring

7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection to the DCC module is made directly from the output of the N2HETx module (from the input of the output buffer).

For more information on DCC see Section 6.7.3.

7.4.6 Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. See the device specific technical reference manual for more details on the "N2HET Pin Disable" feature.

GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin Disable" input for N2HET2.

7.4.7 High-End Timer Transfer Unit (HTU)

A High-End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or from main memory. An MPU is built into the HTU.

7.4.7.1 Features

  • CPU and DMA independent
  • Master Port to access system memory
  • 8 control packets supporting dual buffer configuration
  • Control packet information is stored in RAM protected by parity
  • Event synchronization (HET transfer requests)
  • Supports 32- or 64-bit transactions
  • Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64 bit)
  • One shot, circular and auto switch buffer transfer modes
  • Request lost detection

7.4.7.2 Trigger Connections

Table 7-14 HTU1 Request Line Connection

MODULES REQUEST SOURCE HTU1 REQUEST
N2HET1 HTUREQ[0] HTU1 DCP[0]
N2HET1 HTUREQ[1] HTU1 DCP[1]
N2HET1 HTUREQ[2] HTU1 DCP[2]
N2HET1 HTUREQ[3] HTU1 DCP[3]
N2HET1 HTUREQ[4] HTU1 DCP[4]
N2HET1 HTUREQ[5] HTU1 DCP[5]
N2HET1 HTUREQ[6] HTU1 DCP[6]
N2HET1 HTUREQ[7] HTU1 DCP[7]

Table 7-15 HTU2 Request Line Connection

MODULES REQUEST SOURCE HTU2 REQUEST
N2HET2 HTUREQ[0] HTU2 DCP[0]
N2HET2 HTUREQ[1] HTU2 DCP[1]
N2HET2 HTUREQ[2] HTU2 DCP[2]
N2HET2 HTUREQ[3] HTU2 DCP[3]
N2HET2 HTUREQ[4] HTU2 DCP[4]
N2HET2 HTUREQ[5] HTU2 DCP[5]
N2HET2 HTUREQ[6] HTU2 DCP[6]
N2HET2 HTUREQ[7] HTU2 DCP[7]

7.5 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

7.5.1 Features

Features of the DCAN module include:

  • Supports CAN protocol version 2.0 part A, B
  • Bit rates up to 1 Mbps
  • The CAN kernel can be clocked by the oscillator for baud-rate generation.
  • 64 mailboxes on each DCAN
  • Individual identifier mask for each message object
  • Programmable FIFO mode for message objects
  • Programmable loop-back modes for self-test operation
  • Automatic bus on after Bus-Off state by a programmable 32-bit timer
  • Message RAM protected by parity
  • Direct access to Message RAM during test mode
  • CAN Rx / Tx pins configurable as general purpose IO pins
  • Message RAM Auto Initialization
  • DMA support

For more information on the DCAN, see the RM48x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU503).

7.5.2 Electrical and Timing Specifications

Table 7-16 Dynamic Characteristics for the DCANx TX and RX Pins

PARAMETER MIN MAX UNIT
td(CANnTX) Delay time, transmit shift register to CANnTX pin(1) 15 ns
td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns
(1) These values do not include rise/fall times of the output buffer.

7.6 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The hardware features of the SCI are augmented to achieve LIN compatibility.

The SCI module is a Universal Asynchronous Receiver-Transmitter (UART) that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.

The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-master/multiple-slave with a message identification for multicast transmission between any network nodes.

7.6.1 LIN Features

The following are features of the LIN module:

  • Compatible to LIN 1.3, 2.0, and 2.1 protocols
  • Multibuffered receive and transmit units DMA capability for minimal CPU intervention
  • Identification masks for message filtering
  • Automatic Master Header Generation
    • Programmable Synch Break Field
    • Synch Field
    • Identifier Field
  • Slave Automatic Synchronization
    • Synch break detection
    • Optional baudrate update
    • Synchronization Validation
  • 231 programmable transmission rates with 7 fractional bits
  • Error detection
  • 2 Interrupt lines with priority encoding

7.7 Serial Communication Interface (SCI)

7.7.1 Features

  • Standard UART communication
  • Supports full- or half-duplex operation
  • Standard nonreturn to zero (NRZ) format
  • Double-buffered receive and transmit functions
  • Configurable frame format of 3 to 13 bits per character based on the following:
    • Data word length programmable from 1 to 8 bits
    • Additional address bit in address-bit mode
    • Parity programmable for zero or 1 parity bit, odd or even parity
    • Stop programmable for 1 or 2 stop bits
  • Asynchronous or isosynchronous communication modes
  • Two multiprocessor communication formats allow communication between more than two devices.
  • Sleep mode is available to free CPU resources during multiprocessor communication.
  • The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate selection.
  • Four error flags and five status flags provide detailed information regarding SCI events.
  • Capability to use DMA for transmit and receive data.

7.8 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between the RM4x microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus™. This module will support any slave or master I2C compatible device.

7.8.1 Features

The I2C has the following features:

  • Compliance to the Philips I2C-bus specification, v2.1 (The I2C Specification, Philips document number 9398 393 40011)
    • Bit/Byte format transfer
    • 7-bit and 10-bit device addressing modes
    • General call
    • START byte
    • Multimaster transmitter/ slave receiver mode
    • Multimaster receiver/ slave transmitter mode
    • Combined master transmit/receive and receive/transmit mode
    • Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
  • Free data format
  • Two DMA events (transmit and receive)
  • DMA event enable/disable capability
  • Seven interrupts that can be used by the CPU
  • Module enable/disable capability
  • The SDA and SCL are optionally configurable as general-purpose I/O
  • Slew rate control of the outputs
  • Open-drain control of the outputs
  • Programmable pullup/pulldown capability on the inputs
  • Supports Ignore NACK mode

NOTE

This I2C module does not support:

  • High-speed (HS) mode
  • C-bus compatibility mode
  • The combined format in 10-bit address mode (the I2C module sends the slave address second byte every time it sends the slave address first byte)

7.8.2 I2C I/O Timing Specifications

Table 7-17 I2C Signals (SDA and SCL) Switching Characteristics(1)

PARAMETER STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
tc(I2CCLK) Cycle time, Internal Module clock for I2C, prescaled from VCLK 75.2 149 75.2 149 ns
f(SCL) SCL Clock frequency 0 100 0 400 kHz
tc(SCL) Cycle time, SCL 10 2.5 µs
tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs
th(SCLL-SDAL) Hold time, SCL low after SDA low (for a repeated START condition) 4 0.6 µs
tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
tw(SCLH) Pulse duration, SCL high 4 0.6 µs
tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 ns
th(SDA-SCLL) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45(2) 0 0.9 µs
tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs
tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
Cb(3) Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
(3) Cb = The total capacitance of one bus line in pF.
RM48L930 RM48L730 RM48L530 i2c_timing_pns160.gifFigure 7-8 I2C Timings

NOTE

  • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
  • The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
  • A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
  • Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

7.9 Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and analog-to-digital converters.

7.9.1 Features

Both Standard and MibSPI modules have the following features:

  • 16-bit shift register
  • Receive buffer register
  • 11-bit baud clock generator
  • SPICLK can be internally-generated (master mode) or received from an external clock source (slave mode)
  • Each word transferred can have a unique format
  • SPI I/Os not used in the communication can be used as digital input/output signals

Table 7-18 MibSPI/SPI Configurations

MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2 SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4 SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA

7.9.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer group with variable number of buffers each.

7.9.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a selectable trigger source. For example, up to 15 trigger sources are available which can be used by each transfer group. These trigger options are listed in Table 7-19 for MIBSPI1, Section 7.9.3.2 for MIBSPI3 and Section 7.9.3.3 for MibSPI5.

7.9.3.1 MIBSPI1 Event Trigger Hookup

Table 7-19 MIBSPI1 Event Trigger Hookup

EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger source.

7.9.3.2 MIBSPI3 Event Trigger Hookup

Table 7-20 MIBSPI3 Event Trigger Hookup

EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 HET[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger source.

7.9.3.3 MIBSPI5 Event Trigger Hookup

Table 7-21 MIBSPI5 Event Trigger Hookup

EVENT # TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin + selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI5 transfers; there is no multiplexing on the input connections.

7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 7-22 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK(4) 40 256tc(VCLK) ns
2(5) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
3(5) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
4(5) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 6 ns
td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 6
5(5) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC) – 4 ns
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC) – 4
6(5) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) tf(SPC) + 2.2 ns
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) tr(SPC) + 2.2
7(5) th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) 10 ns
th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) 10
8(6) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 ns
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5
Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY Hold time SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 ns
Hold time SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11
10 tSPIENA SPIENAn Sample point (C2TDELAY+1) * tc(VCLK) - tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
RM48L930 RM48L730 RM48L530 master_mode_external_timing_phase0_pns160.gifFigure 7-9 SPI Master Mode External Timing (CLOCK PHASE = 0)
RM48L930 RM48L730 RM48L530 master_mode_chip_select_phase0_pns160.gifFigure 7-10 SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

Table 7-23 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK (4) 40 256tc(VCLK) ns
2(5) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
3(5) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
4(5) tv(SIMO-SPCH)M Valid time, SPICLK high after SPISIMO data valid (clock polarity = 0) 0.5tc(SPC)M – 6 ns
tv(SIMO-SPCL)M Valid time, SPICLK low after SPISIMO data valid (clock polarity = 1) 0.5tc(SPC)M – 6
5(5) tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC) – 4 ns
tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC) – 4
6(5) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) tr(SPC) + 2.2 ns
tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) tf(SPC) + 2.2
7(5) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 10 ns
tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 10
8(6) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 ns
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5
Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY Hold time SPICLK low until CS inactive (clock polarity = 0) T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 ns
Hold time SPICLK high until CS inactive (clock polarity = 1) T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11
10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)* tc(VCLK) - tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
RM48L930 RM48L730 RM48L530 master_mode_external_timing_phase1_pns160.gifFigure 7-11 SPI Master Mode External Timing (CLOCK PHASE = 1)
RM48L930 RM48L730 RM48L530 master_mode_chip_select_phase1_pns160.gifFigure 7-12 SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

7.9.5 SPI Slave Mode I/O Timings

Table 7-24 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 20 ns
td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 4 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 4
7(6) th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 2 ns
th(SPCH-SIMO)S Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) 2
8 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 22 ns
td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) + 22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+27 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
RM48L930 RM48L730 RM48L530 slave_mode_external_timing_phase0_pns160.gifFigure 7-13 SPI Slave Mode External Timing (CLOCK PHASE = 0)
RM48L930 RM48L730 RM48L530 slave_mode_enable_timing_phase0_pns160.gifFigure 7-14 SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

Table 7-25 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SOMI-SPCL)S Dealy time, SPISOMI data valid after SPICLK low (clock polarity = 0) trf(SOMI) + 20 ns
td(SOMI-SPCH)S Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4
7(6) tv(SPCH-SIMO)S High time, SPISIMO data valid after SPICLK high (clock polarity = 0) 2 ns
tv(SPCL-SIMO)S High time, SPISIMO data valid after SPICLK low (clock polarity = 1) 2
8 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22 ns
td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+ 27 ns
10 td(SCSL-SOMI)S Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) tc(VCLK) 2tc(VCLK)+trf(SOMI)+ 28 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
RM48L930 RM48L730 RM48L530 slave_mode_external_timing_phase1_pns160.gifFigure 7-15 SPI Slave Mode External Timing (CLOCK PHASE = 1)
RM48L930 RM48L730 RM48L530 slave_mode_enable_timing_phase1_pns160.gifFigure 7-16 SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

7.10 Universal Serial Bus (USB) Host and Device Controllers

7.10.1 Features

This device provides several varieties of USB functionality, including:

  • One full-speed USB device port compatible with the USB Specification Revision 2.0 and USB Specification Revision 1.1
  • Two USB host ports compatible with USB Specification Revision 2.0, which is based on the OHCI Specification For USB Release 1.0.

7.10.2 Electrical and Timing Specifications

Table 7-26 Full-Speed USB Interface Timing Requirements(1)

NO. MIN MAX UNIT
FSU20 td(VPL, VML) Host time duration, USBx.VP and USBx.VM low together during transition(2) 15 ns
Device time duration, USBx.VP and USBx.VM low together during transition 15
FSU21 td(VPH, VMH) Host time duration, USBx.VP and USBx.VM high together during transition(2) 15 ns
Device time duration, USBx.VP and USBx.VM high together during transition 15
(1) The capacitive loading is equivalent to 15 pF.
(2) Applies to both host ports, USB1 and USB2

Table 7-27 Full-Speed USB Interface Switching Characteristics(1)

NO. PARAMETER MIN MAX UNIT
FSU15 td(TXENL–DATV) Host delay time USBx.TXEN active to USBx.TXDAT valid(2) –2.1 2.2 ns
Device delay time USBx.TXEN active to USBx.TXDAT valid 0.6 7
FSU16 td(TXENL–SE0V) Host delay time USBx.TXEN active to USBx.TXSE0 valid(2) –2.0 2.5 ns
Device delay time USBx.TXEN active to USBx.TXSE0 valid –1.9 1.0
FSU17 ts(DAT–SE0) Host skew between USBx.TXDAT and USBx.TXSE0 transition(2) 0 1.7 ns
Device skew between USBx.TXDAT and USBx.TXSE0 transition 0 7.6
FSU18 td(TXENH–DATI) Host delay time USBx.TXEN inactive to USBx.TXDAT invalid(2) –2.2 1.8 ns
Device delay time USBx.TXEN inactive to USBx.TXDAT invalid 0.8 7.1
FSU19 td(TXENH–SE0I) Host delay time USBx.TXEN inactive to USBx.TXSE0 invalid(2) –2.1 1.8 ns
Device delay time USBx.TXEN inactive to USBx.TXSE0 invalid –1.9 1.1
(1) The capacitive loading is equivalent to 15 pF.
(2) Applies to both host ports, USB1 and USB2
RM48L930 RM48L730 RM48L530 usb_modes_newnames_spns160.gifFigure 7-17 Full-Speed USB Interface – Transmit and Receive Modes