SLVS077F April   1977  – January 2021 SG2524 , SG3524

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
  7. 7 12
    1. 7.1 Electrical Characteristics
    2. 7.2 Electrical Characteristics — Continued, Both Parts
    3. 7.3 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 17
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Blanking
      2. 9.3.2 Error Amplifier
      3. 9.3.3 Compensation
      4. 9.3.4 Output Circuitry
      5. 9.3.5 Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Synchronous Operation
      2. 9.4.2 Shutdown Circuitry
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1 Synchronous Operation

When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RTCT must be selected for a clock period slightly greater than that of the external clock.

If two or more SGx524 regulators are operated synchronously, all oscillator output terminals must be tied together. The oscillator programmed for the minimum clock period is the master from which all the other SGx524s operate. In this application, the CTRT values of the slaved regulators must be set for a period approximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensure that the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave regulators.