SPNS155I September   2009  – June 2015 SM470R1B1M-HT

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Characteristics
  4. 4 Bare Die
    1. 4.1 Bare Die Information
  5. 5 Pin Configuration and Functions
    1. 5.1 Features
    2. 5.2 Pin Functions (HFQ/HKP Package)
    3. 5.3 Pin Functions (PGE Package)
  6. 6  Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Electrical Characteristics
    5. 6.5  Thermal Characteristics
    6. 6.6  ZPLL and Clock Specifications
    7. 6.7  RST and PORRST Timings
    8. 6.8  JTAG Scan Interface Timing
    9. 6.9  Output Timings
    10. 6.10 Input Timings
    11. 6.11 Flash Timings
    12. 6.12 SPIn Master Mode Timing Parameters
    13. 6.13 SPIn Slave Mode Timing Parameters
    14. 6.14 SCIN Isosynchronous Mode Timings - Internal Clock
    15. 6.15 SCIN Isosynchronous Mode Timings - External Clock
    16. 6.16 I2C Timing
    17. 6.17 Standard Can Controller (SCC) Mode Timings
    18. 6.18 Expansion Bus Module Timing
    19. 6.19 Multi-Buffered A-to-D Converter (MibADC)
  7. 7 Parameter Measurement Information
    1. 7.1 External Reference Resonator/Crystal Oscillator Clock Option
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 MibADC
        1. 8.1.1.1 MibADC Event Trigger Enhancements
      2. 8.1.2 JTAG Interface
      3. 8.1.3 High-End Timer (HET) Timings
        1. 8.1.3.1 Minimum PWM Output Pulse Width
        2. 8.1.3.2 Minimum Input Pulses that can be Captured
      4. 8.1.4 Interrupt Priority (IEM to CIM)
      5. 8.1.5 Expansion Bus Module (EBM)
    2. 8.2 Memory
      1. 8.2.1 Memory Selects
        1. 8.2.1.1 JTAG Security Module
        2. 8.2.1.2 Memory Security Module
        3. 8.2.1.3 RAM
        4. 8.2.1.4 F05 Flash
          1. 8.2.1.4.1 Flash Protection Keys
          2. 8.2.1.4.2 Flash Read
          3. 8.2.1.4.3 Flash Pipeline Mode
          4. 8.2.1.4.4 Flash Program and Erase
          5. 8.2.1.4.5 HET RAM
          6. 8.2.1.4.6 Peripheral Selects and Base Addresses
          7. 8.2.1.4.7 Direct-Memory Access (DMA)
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Identification Code Register
      2. 9.1.2 Timing Parameter Symbology
    2. 9.2 Development Support
    3. 9.3 Device Nomenclature
    4. 9.4 Documentation Support
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

8 Detailed Description

8.1 Overview

8.1.1 MibADC

The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a 10-bit digital value.

The B1M MibADC module can function in two modes: compatibility mode, where its programmer's model is compatible with the SM470R1x ADC module and its digital results are stored in digital result registers; or in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts or by the DMA.

8.1.1.1 MibADC Event Trigger Enhancements

The MibADC includes two major enhancements over the event-triggering capability of the SM470R1x ADC.

  • Both group 1 and the event group can be configured for event-triggered operation, providing up to two event-triggered groups.
  • The trigger source and polarity can be selected individually for both group1 and the event group from the options identified in Table 8-1.

Table 8-1 MibADC Event Hookup Configuration

EVENT NO. SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] OR EVSRC[1:0])		 SIGNAL PIN NAME
EVENT1 00 ADEVT
EVENT2 01 HET18
EVENT3 10 Reserved
EVENT4 11 Reserved

For group1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are configured via the event group source select bits (EVSRC[1:0]) in the AD event source register (ADEVTSRC[1:0]).

For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (SPNU206).

8.1.2 JTAG Interface

There are two main test access ports (TAPs) on the device:

  • SM470R1x CPU TAP
  • Device TAP for factory test

Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 8-1.

SM470R1B1M-HT jtag_if_tdz046.gifFigure 8-1 JTAG Interface

8.1.3 High-End Timer (HET) Timings

8.1.3.1 Minimum PWM Output Pulse Width

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.

Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK

For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33 ns

8.1.3.2 Minimum Input Pulses that can be Captured

The input pulse width must be greater or equal to the low resolution clock period (LRP), that is, the HET loop (the HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.

Therefore, the minimum input pulse width = LRP(min) = hr(min) × lr(min)/SYSCLK = 1 × 1/SYSCLK

For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 × 1/30 = 33.33 ns

NOTE

Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is, the captured value gives the number of HRP clocks inside the pulse.)

Abbreviations:

hr = HET high resolution divide rate = 1, 2, 3,...63, 64

lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32

High resolution clock period = HRP = hr/SYSCLK

Loop resolution clock period = LRP = hr × lr/SYSCLK

8.1.4 Interrupt Priority (IEM to CIM)

Interrupt requests originating from the B1M peripheral modules (that is, SPI1 or SPI2; SCI1 or SCI2; RTI; and so forth) are assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS module.

Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel between sources.

The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can be programmed in the CIM to be of either type:

  • Fast interrupt request (FIQ)
  • Normal interrupt request (IRQ)

The CIM prioritizes interrupts. The precedence of request channels decrease with ascending channel order in the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their associated modules, see Table 8-2.

Table 8-2 Interrupt Priority (IEM and CIM)

MODULES INTERRUPT SOURCES DEFAULT CIM INTERRUPT LEVEL/CHANNEL IEM CHANNEL
SPI1 SPI1 end-transfer/overrun 0 0
RTI COMP2 interrupt 1 1
RTI COMP1 interrupt 2 2
RTI TAP interrupt 3 3
SPI2 SPI2 end-transfer/overrun 4 4
GIO GIO interrupt A 5 5
Reserved 6 6
HET HET interrupt 1 7 7
I2C1 I2C1 interrupt 8 8
SCI1/SCI2 SCI1 or SCI2 error interrupt 9 9
SCI1 SCI1 receive interrupt 10 10
Reserved 11 11
I2C2 I2C2 interrupt 12 12
HECC1 HECC1 interrupt A 13 13
SCC SCC interrupt A 14 14
Reserved 15 15
MibADC MibADC end event conversion 16 16
SCI2 SCI2 receive interrupt 17 17
DMA DMA interrupt 0 18 18
I2C3 I2C3 interrupt 19 19
SCI1 SCI1 transmit interrupt 20 20
System SW interrupt (SSI) 21 21
Reserved 22 22
HET HET interrupt 2 23 23
HECC1 HECC1 interrupt B 24 24
SCC SCC interrupt B 25 25
SCI2 SCI2 transmit interrupt 26 26
MibADC MibADC end Group 1 conversion 27 27
DMA DMA Interrupt 1 28 28
GIO GIO interrupt B 29 29
MibADC MibADC end Group 2 conversion 30 30
SCI3 SCI3 error interrupt 31 31
Reserved 31 32–37
HECC2 HECC2 interrupt A 31 38
HECC2 HECC2 interrupt B 31 39
SCI3 SCI3 receive interrupt 31 40
SCI3 SCI3 transmit interrupt 31 41
I2C4 I2C4 interrupt 31 42
I2C5 I2C5 interrupt 31 43
Reserved 31 44–47

For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (SPNU211). For more detailed functional information on the CIM, see the TMS470R1x System Module Reference Guide (SPNU189).

8.1.5 Expansion Bus Module (EBM)

The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output pins and expansion bus interface pins. This module supports the multiplexing of the GIO and the expansion bus interface functions. The module also supports 8- and 16- bit expansion bus memory interface mappings as well as mapping of the following expansion bus signals:

  • 27-bit address bus (EBADDR[26:0] for x8, 19-bit address bus (EBADDR[18:0] for x16
  • 8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])
  • 2 write strobes (EBWR[1:0])
  • 2 memory chip selects (EBCS[6:5])
  • 1 output enable (EBOE)
  • 1 external hold signal for interfacing to slow memories (EBHOLD)
  • 1 DMA request line (EBDMAREQ[0])

Table 8-3 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of these pins varies depending on the memory mode.

Table 8-3 Expansion Bus MUX Mapping(1)

GIO EXPANSION BUS MODULE PINS
x8(2) x16(2)
GIOB[0] EBDMAREQ[0] EBDMAREQ[0]
GIOC[0] EBOE EBOE
GIOC[2:1] EBWR[1:0] EBWR[1:0]
GIOC[4:3] EBCS[6:5] EBCS[6:5]
GIOD[5:0] EBADDR[5:0] EBADDR[5:0]
GIOE[7:0] EBDATA[7:0] EBDATA[7:0]
GIOF[7:0] EBADDR[13:6] EBDATA[15:8]
GIOG[7:0] EBADDR[21:14] EBADDR[13:6]
GIOH[5] EBHOLD EBHOLD
I2C5SDA EBADDR[26] EBADDR[18]
I2C5SCL EBADDR[25] EBADDR[17]
I2C4SCL EBADDR[24] EBADDR[16]
I2C4SDA EBADDR[23] EBADDR[15]
GIOH[0] EBADDR[22] EBADDR[14]
(1) For more detailed information, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide (SPNU222) and the TMS470R1x General Purpose Input/Output Reference Guide (SPNU192).
(2) X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.

Table 8-4 lists the names of the expansion bus interface signals and their functions.

Table 8-4 Expansion Bus Pins

PIN DESCRIPTION
EBDMAREQ Expansion bus DMA request
EBOE Expansion bus pin enable
EBWR Expansion bus write strobe EBWR[1] controls EBDATA[15:8] and EBWR[0] controls EBDATA[7:0]
EBCS Expansion bus chip select
EBADDR Expansion bus address pins
EBDATA Expansion bus data pins
EBHOLD Expansion bus hold: An external device may assert this signal to add wait states to an expansion bus transaction.

8.2 Memory

Figure 8-2 shows the memory map of the B1M device.

SM470R1B1M-HT mem_map_pns109.gif
A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not part of the memory map.
Figure 8-2 SM470R1B1M Memory Map

8.2.1 Memory Selects

Memory selects allow the user to address memory arrays (that is, flash, RAM, and HET RAM) at user-defined addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.

The base address of each memory select is configurable to any memory address boundary that is a multiple of the decoded block size. For more information on how to control and configure these memory select registers, see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (SPNU189).

For the memory selection assignments and the memory selected, see Table 8-5.

Table 8-5 SM470R1B1M Memory Selection Assignment

MEMORY SELECT MEMORY SELECTED
(ALL INTERNAL)		 MEMORY
SIZE(1)		 MPU MSM MEMORY BASE ADDRESS REGISTER STATIC MEM CTL REGISTER
0 (fine) FLASH/ROM 1 M NO YES MFBAHR0 and MFBALR0
1 (fine) FLASH/ROM NO YES MFBAHR1 and MFBALR1
2 (fine) RAM 64 K(2) YES YES MFBAHR2 and MFBALR2
3 (fine) RAM YES YES MFBAHR3 and MFBALR3
4 (fine) HET RAM 1 K NO NO MFBAHR4 and MFBALR4 SMCR1
5 (coarse) CS[5]/GIOC[3] 512K x 8 (512KB)
256K x 16 (512KB) 		NO NO MCBAHR2 and MCBALR2 SMCR5
6 (coarse) CS[6]/GIOC[4] 512K x 8 (512KB)
256K x 16 (512KB) 		NO NO MCBAHR3 and MCBALR3 SMCR6
(1) x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
(2) The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the memory-base address register.

8.2.1.1 JTAG Security Module

The B1M device includes a JTAG security module to provide maximum security to the memory contents. The visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory. For the B1M, the visible unlock code is in the OTP sector at address 0x0000_01F8.

8.2.1.2 Memory Security Module

The B1M device also includes a memory security module (MSM) to provide additional security and flexibility to the memory contents' protection. The password for unlocking the MSM is located in the four words just before the flash protection keys.

8.2.1.3 RAM

The B1M device contains 64KB of internal static RAM configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. This B1M RAM is implemented in one 64KB array selected by two memory-select signals. This B1M configuration imposes an additional constraint on the memory map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the size of the physical RAM (that is, 64K bytes for the B1M device). The B1M RAM is addressed through memory selects 2 and 3.

The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an operating system while allowing access to the current task. For more detailed information on the MPU portion of the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference Guide (SPNU189).

8.2.1.4 F05 Flash

The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase functions. See the Flash read and Flash program and erase sections.

8.2.1.4.1 Flash Protection Keys

The B1M device provides flash protection keys. These four 32-bit protection keys prevent program/erase/compaction operations from occurring until after the four protection keys have been matched by the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B1M are located in the last 4 words of the first 64K sector.

8.2.1.4.2 Flash Read

The B1M flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.

NOTE

The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).

8.2.1.4.3 Flash Pipeline Mode

When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system clock frequency of 30 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).

NOTE

After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other words, the B1M device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will override pipeline mode.

8.2.1.4.4 Flash Program and Erase

The B1M device flash contains two 512KB memory arrays (or banks), for a total of 1MB of flash, and consists of sixteen sectors. These sixteen sectors are sized as follows:

Table 8-6 Sectors

SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS MEMORY ARRAYS
(OR BANKS)
OTP 2KB 0x0000_0000 0x0000_007FF BANK0
(512KB)
0 64KB 0x0000_0000 0x0000_FFFF
1 64KB 0x0001_0000 0x0001_FFFF
2 64KB 0x0002_0000 0x0002_FFFF
3 64KB 0x0003_0000 0x0003_FFFF
4 64KB 0x0004_0000 0x0004_FFFF
5 64KB 0x0005_0000 0x0005_FFFF
6 64KB 0x0006_0000 0x0006_FFFF
7 64KB 0x0007_0000 0x0007_FFFF
0 64KB 0x0008_0000 0x0008_FFFF BANK1
(512KB)
1 64KB 0x0009_0000 0x0009_FFFF
2 64KB 0x000A_0000 0x000A_FFFF
3 64KB 0x000B_0000 0x000B_FFFF
4 64KB 0x000C_0000 0x000C_FFFF
5 64KB 0x000D_0000 0x000D_FFFF
6 64KB 0x000E_0000 0x000E_FFFF
7 64KB 0x000F_0000 0x000F_FFFF

The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit word.

NOTE

The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).

Execution can occur from one bank while programming/erasing any or all sectors of another bank. However, execution cannot occur from any sector within a bank that is being programmed or erased.

NOTE

When the OTP sector is enabled, the rest of flash memory is disabled. The OTP memory can only be read or programmed from code executed out of RAM.

8.2.1.4.5 HET RAM

The B1M device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET RAM is addressed through memory select 4.

8.2.1.4.6 Peripheral Selects and Base Addresses

The B1M device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the SYS module.

Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 8-7.

Table 8-7 B1M Peripherals, System Module, and Flash Base Addresses

CONNECTING MODULE ADDRESS RANGE PERIPHERAL SELECTS
BASE ADDRESS ENDING ADDRESS
SYSTEM 0 x FFFF_FFCC 0 x FFFF_FFFF N/A
RESERVED 0 x FFFF_FF70 0 x FFFF_FFCB N/A
DWD 0xFFFF_FF60 0 x FFFF_FF6F N/A
PSA 0 x FFFF_FF40 0 x FFFF_FF5F N/A
CIM 0 x FFFF_FF20 0 x FFFF_FF3F N/A
RTI 0 x FFFF_FF00 0 x FFFF_FF1F N/A
DMA 0 x FFFF_FE80 0 x FFFF_FEFF N/A
DEC 0 x FFFF_FE00 0 x FFFF_FE7F N/A
RESERVED 0xFFFF_FD80 0xFFFF_FDFF N/A
MMC 0 x FFFF_FD00 0 x FFFF_FD7F N/A
IEM 0 x FFFF_FC00 0 x FFFF_FCFF N/A
RESERVED 0 x FFFF_Fb00 0 x FFFF_FBFF N/A
RESERVED 0 x FFFF_Fa00 0 x FFFF_FAFF N/A
DMA CMD BUFFER 0 x FFFF_F800 0 x FFFF_F9FF N/A
MSM 0xFFFF_F700 0xFFFF_F7FF N/A
RESERVED 0xFFF8_0000 0xFFFF_F6FF N/A
RESERVED 0 x FFF7_FD00 0xFFF7_FFFF PS[0]
HET 0xFFF7_FC00 0xFFF7_FCFF
RESERVED 0xFFF7_F900 0xFFF7_FBFF PS[1]
SPI1 0xFFF7_F800 0xFFF7_F8FF
RESERVED 0xFFF7_F700 0xFFF7_F7FF PS[2]
SCI3 0xFFF7_F600 0xFFF7_F6FF
SCI2 0XFFF7_F500 0XFFF7_F5FF
SCI1 0xFFF7_F400 0xFFF7_F4FF
RESERVED 0xFFF7_F100 0xFFF7_F3FF PS[3]
MibADC 0xFFF7_F000 0xFFF7_F0FF
ECP 0xFFF7_EF00 0xFFF7_EFFF PS[4]
RESERVED 0xFFF7_EE00 0xFFF7_EEFF
EBM 0xFFF7_ED00 0xFFF7_EDFF
GIO 0xFFF7_EC00 0xFFF7_ECFF
HECC2 0xFFF7_EB00 0xFFF7_EBFF PS[5]
0xFFF7_EA00 0xFFF7_EAFF
HECC1 0xFFF7_E900 0xFFF7_E9FF
0xFFF7_E800 0xFFF7_E8FF
HECC2 RAM 0xFFF7_E700 0xFFF7_E7FF PS[6]
0xFFF7_E600 0xFFF7_E6FF
HECC1 RAM 0xFFF7_E500 0xFFF7_E5FF
0xFFF7_E400 0xFFF7_E4FF
RESERVED 0xFFF7_E100 0xFFF7_E3FF PS[7]
SCC 0xFFF7_E000 0xFFF7_E0FF
RESERVED 0xFFF7_DD00 0xFFF7_DFFF PS[8]
SCC RAM 0xFFF7_DC00 0xFFF7_DCFF
I2C4 0xFFF7_DB00 0xFFF7_DBFF PS[9]
I2C3 0xFFF7_DA00 0xFFF7_DAFF
I2C2 0xFFF7_D900 0xFFF7_D9FF
I2C1 0xFFF7_D800 0xFFF7_D8FF
RESERVED 0xFFF7_D600 0xFFF7_D7FF PS[10]
I2C5 0xFFF7_D500 0xFFF7_D5FF
SPI2 0xFFF7_D400 0xFFF7_D4FF
RESERVED 0xFFF7_CC00 0xFFF7_D3FF PS[11] – PS[12]
RESERVED 0xFFF7_C800 0xFFF7_CBFF PS[13]
RESERVED 0xFFF7_C000 0xFFF7_C7FF PS[14] – PS[15]
RESERVED 0xFFF0_0000 0xFFF7_BFFF N/A
FLASH CONTROL REGISTERS 0xFFE8_8000 0xFFE8_BFFF N/A
RESERVED 0xFFF8_4024 0xFFF8_7FFF N/A
MPU CONTROL REGISTERS 0xFFE8_4000 0xFFE8_4023 N/A
RESERVED 0xFFF8_0000 0xFFF8_3FFF N/A

8.2.1.4.7 Direct-Memory Access (DMA)

The direct-memory access (DMA) controller transfers data to and from any specified location in the B1M memory map (except for restricted memory locations like the system control registers area). The DMA manages up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA controller is connected to both the CPU and peripheral buses, enabling these data transfers to occur in parallel with CPU activity and thus maximizing overall system performance.

Although the DMA controller has two possible configurations, for the B1M device, the DMA controller configuration is 32 control packets and 16 channels.

For the B1M DMA request hardwired configuration, see Table 8-8.

Table 8-8 DMA Request Lines Connections(1)

MODULES DMA REQUEST INTERRUPT SOURCES DMA CHANNEL
EBM Expansion Bus DMA request EBDMAREQ[0] DMAREQ[0]
SPI1/I2C4 SPI1 end-receive/I2C4 read SPI1DMA0/I2C4DMA0 DMAREQ[1]
SPI1/I2C4 SPI1 end-transmit/I2C4 write SPI1DMA1/I2C4DMA1 DMAREQ[2]
MibADC/I2C1 ADC EV/I2C1 read MibADCDMA0/I2C1DMA0 DMAREQ[3]
MibADC/SCI1/I2C5 ADC G1/SCI1 end-receive/I2C5 read MibADCDMA1/SCI1DMA0/I2C5DMA0 DMAREQ[4]
MibADC/SCI1/I2C5 ADC G2/SCI1 end-transmit/I2C5 write MibADCDMA2/SCI1DMA1/I2C5DMA1 DMAREQ[5]
I2C1 I2C1 write I2C1DMA1 DMAREQ[6]
SCI3/SPI2 SCI3 end-receive/SPI2 end-receive SCI3DMA0/SPI2DMA0 DMAREQ[7]
SCI3/SPI2 SCI3 end-transmit/SPI2 end-transmit SCI3DMA01SPI2DMA1 DMAREQ[8]
I2C2 I2C2 read end-receive I2C2DMA0 DMAREQ[9]
I2C2 I2C2 write end-transmit I2C2DMA1 DMAREQ[10]
I2C3 I2C3 read I2C3DMA0 DMAREQ[11]
I2C3 I2C3 write I2C3DMA1 DMAREQ[12]
Reserved DMAREQ[13]
SCI2 SCI2 end-receive SCI2DMA0 DMAREQ[14]
SCI2 SCI2 end-transmit SCI2DMA1 DMAREQ[15]
(1) For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a given application. The device has software control to ensure that there are no conflicts between requesting modules.

Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable, and the channels determine the priority level of the interrupt.

DMA transfers occur in one of two modes:

  • Non-request mode (used when transferring from memory to memory)
  • Request mode (used when transferring from memory to peripheral)

For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (SPNU194).