SPNS155 Data sheet

SPNS155I September 2009 – June 2015 SM470R1B1M-HT

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PGE|144
- MTQF017A
HFQ|84
- MCQF017A

Thermal pad, mechanical data (Package|Pins)

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, A version (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_CC⁽²⁾	–0.3	2.5	V
Supply voltage	V_CCIO, V_CCAD, V_CCP (flash pump)⁽²⁾	–0.3	4.1	V
Input voltage	All 5-V tolerant input pins	–0.3	6.0	V
Input voltage	All other input pins	–0.3	4.1	V
Input clamp current	I_IK (V_I < 0 or V_I > V_CCIO) All pins except ADIN[0:11], PORRST, TRST, TEST, and TCK		±20	mA
Input clamp current	I_IK (V_I < 0 or V_I > V_CCAD) ADIN[0:11]		±10	mA
Operating free-air temperature, T_A	HFQ/HKP package	–55	220	°C
Operating free-air temperature, T_A	PGE package	–55	150	°C
Storage temperature, T_stg		–55	220	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to their associated grounds.

6.2 ESD Ratings

			VALUE	UNIT
SM470R1B1M-HT in CFP Package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	750	V
SM470R1B1M-HT in LQFP Package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions⁽¹⁾

			MIN	NOM	MAX	UNIT
V_CC	Digital logic supply voltage (Core)	SYSCLK = 48 MHz (pipeline mode enabled)	1.71		2.05	V
V_CC	Digital logic supply voltage (Core)	SYSCLK = 60 MHz (pipeline mode enabled)	1.81		2.05	V
V_CCIO	Digital logic supply voltage (I/O)		3		3.6	V
V_CCAD	ADC supply voltage		3		3.6	V
V_CCP	Flash pump supply voltage		3		3.6	V
V_SS	Digital logic supply ground			0		V
V_SSAD	ADC supply ground⁽¹⁾		–0.1		0.1	V
T_A	Operating free-air temperature	HFQ/HKP package	–55		220	°C
T_A	Operating free-air temperature	PGE package	–55		150	°C

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD.

6.4 Electrical Characteristics

Minimum and maximum parameters are characterized over the operating temperature range unless otherwise noted, but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. ⁽¹⁾

PARAMETER			TEST CONDITIONS	MIN	TYP⁽²⁾	MAX	UNIT
V_hys	Input hysteresis				0.15		V
V_IL	Low-level input voltage	All inputs⁽³⁾		–0 .3		0.8	V
V_IH	High-level input voltage	All inputs		2		V_CCIO + 0. 3	V
	Input threshold voltage	AWD only⁽⁴⁾		1.35		1.8
	Input threshold voltage	OSCIN with digital input only		0.7 V_CC		V_CC + 0.3
V_OL	Low-level output voltage⁽⁵⁾		I_OL = I_OL MAX			0.2 V_CCIO	V
V_OL	Low-level output voltage⁽⁵⁾		I_OL = 50 µA			0.2	V
V_OH	High-level output voltage⁽⁵⁾		I_OH = I_OH MIN	0.8 V_CCIO			V
V_OH	High-level output voltage⁽⁵⁾		I_OH = 50 µA	V_CCIO – 0.2			V
I_IC	Input clamp current (I/O pins)⁽⁶⁾		V_I < V_SSIO – 0. 3 or V_I > V_CCIO + 0. 3	–2		2	mA
I_I	Input current (3.3 V input pins)	I_IL Pulldown	V_I = V_SS	–1		1	µA
		I_IH Pulldown	V_I = V_CCIO	5		100
		I_IL Pullup	V_I = V_SS	–100		–5
		I_IH Pullup	V_I = V_CCIO	–1		1
		All other pins	No pullup or pulldown	–1		1
	Input current (5 V tolerant input pins)		V_I = V_SS	–1		1	µA
			V_I = V_CCIO	1		5
			V_I = 5 V	5		25
			V_I = 5.5 V	25		50
I_OL	Low-level output current	CLKOUT, AWD, TDI, TDO, TMS, TMS2	V_OL = V_OL MAX			8	mA
		RST				4
		All other 3.3 V I/O⁽⁷⁾				2
		5 V tolerant				4
I_OH	High-level output current	CLKOUT, TDI, TDO, TMS, TMS2	V_OH = V_OH MIN	–8			mA
		RST		–4
		All other 3.3 V I/O⁽⁷⁾		–2
		5 V tolerant		–4
I_CC	V_CC Digital supply current (operating mode)		SYSCLK = 48 MHz, ICLK = 24 MHz, V_CC = 2.05 V			110	mA
	V_CC Digital supply current (operating mode)		SYSCLK = 60 MHz, ICLK = 30 MHz, V_CC = 2.05 V			125	mA
	V_CC Digital supply current (standby mode)⁽⁸⁾⁽⁹⁾		OSCIN = 5 MHz, V_CC = 2.05 V			28	mA
	V_CC Digital supply current (halt mode)⁽⁸⁾⁽⁹⁾		All frequencies, V_CC = 2.05 V			700	µA
I_CCIO	V_CCIO Digital supply current (operating mode)		No DC load, V_CCIO = 3.6 V⁽¹⁰⁾			20	mA
	V_CCIO Digital supply current (standby mode)⁽⁹⁾		No DC load, V_CCIO = 3.6 V⁽¹⁰⁾			250	µA
	V_CCIO Digital supply current (halt mode)⁽⁹⁾		No DC load, V_CCIO = 3.6 V⁽¹⁰⁾			225	µA
I_CCAD	V_CCAD supply current (operating mode)		All frequencies, V_CCAD = 3.6 V			15	mA
	V_CCAD supply current (standby mode)		All frequencies, V_CCAD = 3.6 V			10	µA
	V_CCAD supply current (halt mode)		All frequencies, V_CCAD = 3.6 V			10	µA
I_CCP	V_CCP pump supply current		SYSCLK = 48 MHz, V_CCP = 3.6 V read operation			45	mA
			SYSCLK = 60 MHz, V_CCP = 3.6 V read operation			55	mA
			V_CCP = 3.6 V program and erase			70	mA
			V_CCP = 3.6 V standby mode operation⁽⁸⁾			10	µA
			V_CCP = 3.6 V halt mode operation⁽⁸⁾			10	µA
C_I	Input capacitance				2		pF
C_O	Output capacitance				3		pF

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2) The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal V_CC, V_CCIO, or V_CCAD, room temperature.

(3) This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST Timings section.

(4) These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide (SPNU189).

(5) V_OL and V_OH are linear with respect to the amount of load current (I_OL/I_OH) applied.

(6) Parameter does not apply to input-only or output-only pins.

(7) Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Pin Functions table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value will always be low.

(8) For flash banks/pumps in sleep mode.

(9) For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.

(10) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤0.2 V. All pullup inputs ≥ V_CCIO – 0.2 V.

6.5 Thermal Characteristics

THERMAL METRIC⁽¹⁾		SM470R1B1M-HT		UNIT
		HFQ (CQFP) OR HKP (CFP)	PGE (LQFP)
		64 PINS	144 PINS
R_θJA	Junction-to-ambient thermal resistance	N/A	38.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	N/A	5.7	°C/W
R_θJB	Junction-to-board thermal resistance	152.0148	19.7	°C/W
ψ_JT	Junction-to-top characterization parameter	N/A	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	N/A	19.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	5.4898	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

1. See data sheet for absolute maximum and minimum recommended operating conditions.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

Figure 6-1 SM470R1B1M-HT Life Expectancy Curve (HFQ/HKP Package)

1. See data sheet for absolute maximum and minimum recommended operating conditions.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

3. Device is qualified for 1000 hour operation at 150°C. Device is functional at 175°C, but at reduced operating life.

Figure 6-2 SM470R1B1M-HT Wirebond Life Derating Chart (PGE Package)

6.6 ZPLL and Clock Specifications

Table 6-1 Timing Requirements for ZPLL Circuits Enabled or Disabled⁽¹⁾

		MIN	TYP	MAX	UNIT
ƒ_(OSC)	Input clock frequency	4		10	MHz
t_c(OSC)	Cycle time, OSCIN	100			ns
t_w(OSCIL)	Pulse duration, OSCIN low	15			ns
t_w(OSCIH)	Pulse duration, OSCIN high	15			ns
ƒ_(OSCRST)	OSC FAIL frequency⁽²⁾		53		kHz

(1) Not production tested.

(2) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (SPNU189).

Table 6-2 Switching Characteristics over Recommended Operating Conditions for Clocks⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

PARAMETER		TEST CONDITIONS⁽⁵⁾	MIN	MAX	UNIT
ƒ_(SYS)	System clock frequency⁽⁶⁾	Pipeline mode enabled		60⁽⁷⁾	MHz
ƒ_(SYS)	System clock frequency⁽⁶⁾	Pipeline mode disabled		24	MHz
ƒ_(CONFIG)	System clock frequency - flash config mode			24	MHz
ƒ_(ICLK)	Interface clock frequency	Pipeline mode enabled		30	MHz
ƒ_(ICLK)	Interface clock frequency	Pipeline mode disabled		24	MHz
ƒ_(ECLK)	External clock output frequency for ECP module	Pipeline mode enabled		30	MHz
ƒ_(ECLK)	External clock output frequency for ECP module	Pipeline mode disabled		24	MHz
t_c(SYS)	Cycle time, system clock	Pipeline mode enabled	16.7		ns
t_c(SYS)	Cycle time, system clock	Pipeline mode disabled	41.6		ns
t_c(CONFIG)	Cycle time, system clock - flash config mode		41.6		ns
t_c(ICLK)	Cycle time, interface clock	Pipeline mode enabled	33.3		ns
t_c(ICLK)	Cycle time, interface clock	Pipeline mode disabled	41.6		ns
t_c(ECLK)	Cycle time, ECP module external clock output	Pipeline mode enabled	33.3		ns
t_c(ECLK)	Cycle time, ECP module external clock output	Pipeline mode disabled	41.6		ns

(1) Not production tested.

(2) ƒ_(SYS) = M × ƒ_(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register (GLBCTRL.3).
ƒ_(SYS) = ƒ_(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
ƒ_(ICLK) = ƒ_(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.

(3) ƒ_(ECLK) = ƒ_(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.

(4) Only ZPLL mode is available. FM mode must not be turned on.

(5) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).

(6) Flash Vread must be set to 5 V to achieve maximum system clock frequency.

(7) Operating V_CC range for this system clock frequency is 1.81 to 2.05 V.

Table 6-3 Switching Characteristics over Recommended Operating Conditions for External Clocks⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

(see Figure 6-3 and Figure 6-4)

PARAMETER		TEST CONDITIONS	MIN	UNIT
t_w(COL)	Pulse duration, CLKOUT low	SYSCLK or MCLK⁽⁵⁾	0.5t_c(SYS) – t_f	ns
		ICLK: X is even or 1⁽⁶⁾	0.5t_c(ICLK) – t_f
		ICLK: X is odd and not 1⁽⁶⁾	0.5t_c(ICLK) + 0.5t_c(SYS) – t_f
t_w(COH)	Pulse duration, CLKOUT high	SYSCLK or MCLK⁽⁵⁾	0.5t_c(SYS) – t_r	ns
		ICLK: X is even or 1⁽⁶⁾	0.5t_c(ICLK) – t_r
		ICLK: X is odd and not 1⁽⁶⁾	0.5t_c(ICLK) – 0.5t_c(SYS) – t_r
t_w(EOL)	Pulse duration, ECLK low	N is even and X is even or odd	0.5t_c(ECLK) – t_f	ns
		N is odd and X is even	0.5t_c(ECLK) – t_f
		N is odd and X is odd and not 1	0.5t_c(ECLK) + 0.5t_c(SYS) – t_f
t_w(EOH)	Pulse duration, ECLK high	N is even and X is even or odd	0.5t_c(ECLK) – t_r	ns
		N is odd and X is even	0.5t_c(ECLK) – t_r
		N is odd and X is odd and not 1	0.5t_c(ECLK) – 0.5t_c(SYS) – t_r

(1) Not production tested.

(2) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.

(3) N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.

(4) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.

(5) Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).

(6) Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).

Figure 6-3 CLKOUT Timing Diagram

Figure 6-4 ECLK Timing Diagram

6.7 RST and PORRST Timings

Table 6-4 Timing Requirements for PORRST⁽¹⁾

(see Figure 6-5)

		MIN	MAX	UNIT
V_CCPORL	V_CC low supply level when PORRST must be active during power up		0.6	V
V_CCPORH	V_CC high supply level when PORRST must remain active during power up and become active during power down	1.5		V
V_CCIOPORL	V_CCIO low supply level when PORRST must be active during power up		1.1	V
V_CCIOPORH	V_CCIO high supply level when PORRST must remain active during power up and become active during power down	2.75		V
V_IL	Low-level input voltage after V_CCIO > V_CCIOPORH		0.2 V_CCIO	V
V_IL(PORRST)	Low-level input voltage of PORRST before V_CCIO > V_CCIOPORL		0.5	V
t_su(PORRST)r	Setup time, PORRST active before V_CCIO > V_CCIOPORL during power up	0		ms
t_su(VCCIO)r	Setup time, V_CCIO > V_CCIOPORL before V_CC > V_CCPORL	0		ms
t_h(PORRST)r	Hold time, PORRST active after V_CC > V_CCPORH	1		ms
t_su(PORRST)f	Setup time, PORRST active before V_CC ≤ V_CCPORH during power down	8		µs
t_h(PORRST)rio	Hold time, PORRST active after V_CC > V_CCIOPORH	1		ms
t_h(PORRST)d	Hold time, PORRST active after V_CC < V_CCPORL	0		ms
t_{su(PORRST)fio}	Setup time, PORRST active before V_CC ≤ V_CCIOPORH during power down	0		ns
t_su(VCCIO)f	Setup time, V_CC < V_CCPORL before V_CCIO < V_CCIOPORL	0		ns

(1) Not production tested.

NOTE: V_CCIO > 1.1 V before V_CC > 0.6 V

Figure 6-5 PORRST Timing Diagram

Table 6-5 Switching Characteristics over Recommended Operating Conditions for RST⁽¹⁾⁽²⁾

PARAMETER		MIN	UNIT
t_v(RST)	Valid time, RST active after PORRST inactive	4112t_c(OSC)	ns
t_v(RST)	Valid time, RST active (all others)	8t_c(SYS)	ns
t_fsu	Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump stabilization time)	836t_c(OSC)	ns

(1) Not production tested.

(2) Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

6.8 JTAG Scan Interface Timing

Table 6-6 JTAG Clock Specification 10-MHz and 50-pF Load on TDO Output⁽¹⁾

		MIN	MAX	UNIT
t_c(JTAG)	Cycle time, JTAG low and high period	50		ns
t_{su(TDI/TMS - TCKr)}	Setup time, TDI, TMS before TCK rise (TCKr)	15		ns
t_{h(TCKr -TDI/TMS)}	Hold time, TDI, TMS after TCKr	15		ns
t_{h(TCKf -TDO)}	Hold time, TDO after TCKf	10		ns
t_{d(TCKf -TDO)}	Delay time, TDO valid after TCK fall (TCKf)		45	ns

(1) Not production tested.

Figure 6-6 JTAG Scan Timings

6.9 Output Timings

Table 6-7 Switching Characteristics for Output Timings versus Load Capacitance (C_L)⁽¹⁾

(see Figure 6-7)

PARAMETER			MIN	MAX	UNIT
t_r	Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2	C_L = 15 pF	0.5	2.5	ns
		C_L = 50 pF	1.5	5.0
		C_L = 100 pF	3.0	9.0
		C_L = 150 pF	4.5	12.5
t_f	Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2	C_L = 15 pF	0.5	2.5	ns
		C_L = 50 pF	1.5	5.0
		C_L = 100 pF	3.0	9.0
		C_L = 150 pF	4.5	12.5
t_r	Rise time, RST	C_L = 15 pF	2.5	8	ns
		C_L = 50 pF	5	14
		C_L = 100 pF	9	23
		C_L = 150 pF	13	32
t_r	Rise time, 4-mA, 5-V tolerant pins	C_L = 15 pF	3	10	ns
		C_L = 50 pF	3.5	12
		C_L = 100 pF	7	21
		C_L = 150 pF	9	28
		C_L = 400 pF	18	40
t_f	Fall time, 4-mA, 5-V tolerant pins	C_L = 15 pF	2	8	ns
		C_L = 50 pF	2.5	9
		C_L = 100 pF	8	25
		C_L = 150 pF	11	35
		C_L = 400 pF	20	45
t_r	Rise time, all other output pins	C_L = 15 pF	2.5	10	ns
		C_L = 50 pF	6.0	25
		C_L = 100 pF	12	45
		C_L = 150 pF	18	65
t_f	Fall time, all other output pins	C_L = 15 pF	3	10	ns
		C_L = 50 pF	8.5	25
		C_L = 100 pF	16	45
		C_L = 150 pF	23	65

(1) Not production tested.

Figure 6-7 CMOS-Level Outputs

6.10 Input Timings

Table 6-8 Timing Requirements for Input Timings⁽¹⁾⁽²⁾

(see Figure 6-8)

		MIN	MAX	UNIT
t_pw	Input minimum pulse width	t_c(ICLK) + 10		ns

(1) Not production tested.

(2) t_c(ICLK) = interface clock cycle time = 1/ƒ_(ICLK)

Figure 6-8 CMOS-Level Inputs

6.11 Flash Timings

Table 6-9 Timing Requirements for Program Flash⁽¹⁾⁽²⁾

		MIN	TYP	MAX	UNIT
t_prog(16-bit)	Half word (16-bit) programming time	4	16	200	µs
t_prog(Total)	1MB programming time⁽³⁾		8	32	s
t_{erase(sector)}	Sector erase time, T_A = –40°C to 150°C		1.7		s
t_wec	Write/erase cycles at T_A = –40°C to 85°C	50000			cycles
t_fp(RST)	Flash pump settling time from RST to SLEEP		167t_c(SYS)		ns
t_fp(SLEEP)	Initial flash pump settling time from SLEEP to STANDBY		167t_c(SYS)		ns
t_fp(STANDBY)	Initial flash pump settling time from STANDBY to ACTIVE		84t_c(SYS)		ns

(1) Not production tested.

(2) For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.

(3) The 1MB programming time includes overhead of state machine.

6.12 SPIn Master Mode Timing Parameters

Table 6-10 SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾ (see Figure 6-9)

NO.			MIN	MAX	UNIT
1	t_c(SPC)M	Cycle time, SPInCLK⁽⁵⁾	100	256t_c(ICLK)	ns
2⁽⁶⁾	t_w(SPCH)M	Pulse duration, SPInCLK high (clock polarity = 0)	0.5t_c(SPC)M – t_r	0.5t_c(SPC)M + 5
2⁽⁶⁾	t_w(SPCL)M	Pulse duration, SPInCLK low (clock polarity = 1)	0.5t_c(SPC)M – t_f	0.5t_c(SPC)M + 5
3⁽⁶⁾	t_w(SPCL)M	Pulse duration, SPInCLK low (clock polarity = 0)	0.5t_c(SPC)M – t_f	0.5t_c(SPC)M + 5
3⁽⁶⁾	t_w(SPCH)M	Pulse duration, SPInCLK high (clock polarity = 1)	0.5t_c(SPC)M – t_r	0.5t_c(SPC)M + 5
4⁽⁶⁾	t_{d(SPCH-SIMO)M}	Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)		10
4⁽⁶⁾	t_{d(SPCL-SIMO)M}	Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)		10
5⁽⁶⁾	t_{v(SPCL-SIMO)M}	Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)	t_c(SPC)M – 5 – t_f
5⁽⁶⁾	t_{v(SPCH-SIMO)M}	Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)	t_c(SPC)M – 5 – t_r
6⁽⁶⁾	t_{su(SOMI-SPCL)M}	Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)	6
6⁽⁶⁾	t_{su(SOMI-SPCH)M}	Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)	6
7⁽⁶⁾	t_{v(SPCL-SOMI)M}	Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)	4
7⁽⁶⁾	t_{v(SPCH-SOMI)M}	Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)	4

(1) Not production tested.

(2) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(3) t_c(ICLK) = interface clock cycle time = 1 / ƒ_(ICLK)

(4) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(5) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M ≥(PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(ICLK) ≥ 100 ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 6-9 SPIn Master Mode External Timing (CLOCK PHASE = 0)

Table 6-11 SPIn Master Mode External Timing Parameters⁽¹⁾

(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)⁽²⁾⁽³⁾⁽⁴⁾ (see Figure 6-10)

NO.			MIN	MAX	UNIT
1	t_c(SPC)M	Cycle time, SPInCLK⁽⁵⁾	100	256t_c(ICLK)	ns
2⁽⁶⁾	t_w(SPCH)M	Pulse duration, SPInCLK high (clock polarity = 0)	0.5t_c(SPC)M – t_r	0.5t_c(SPC)M + 5
2⁽⁶⁾	t_w(SPCL)M	Pulse duration, SPInCLK low (clock polarity = 1)	0.5t_c(SPC)M – t_f	0.5t_c(SPC)M + 5
3⁽⁶⁾	t_w(SPCL)M	Pulse duration, SPInCLK low (clock polarity = 0)	0.5t_c(SPC)M – t_f	0.5t_c(SPC)M + 5
3⁽⁶⁾	t_w(SPCH)M	Pulse duration, SPInCLK high (clock polarity = 1)	0.5t_c(SPC)M – t_r	0.5t_c(SPC)M + 5
4⁽⁶⁾	t_{v(SIMO-SPCH)M}	Valid time, SPInCLK high after SPInSIMO data valid (clock polarity = 0)	0.5t_c(SPC)M – 10
4⁽⁶⁾	t_{v(SIMO-SPCL)M}	Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)	0.5t_c(SPC)M – 10
5⁽⁶⁾	t_{v(SPCH-SIMO)M}	Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)	0.5t_c(SPC)M – 5 – t_r
5⁽⁶⁾	t_{v(SPCL-SIMO)M}	Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)	0.5t_c(SPC)M – 5 – t_f
6⁽⁶⁾	t_{su(SOMI-SPCH)M}	Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)	6
6⁽⁶⁾	t_{su(SOMI-SPCL)M}	Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)	6
7⁽⁶⁾	t_{v(SPCH-SOMI)M}	Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)	4
7⁽⁶⁾	t_{v(SPCL-SOMI)M}	Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)	4

(1) Not production tested.

(2) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(3) t_c(ICLK) = interface clock cycle time = 1/ƒ_(ICLK)

(4) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(5) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M ≥ (PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(ICLK) ≥ 100 ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 6-10 SPIn Master Mode External Timing (CLOCK PHASE = 1)

6.13 SPIn Slave Mode Timing Parameters

Table 6-12 SPIn Slave Mode External Timing Parameters⁽¹⁾

(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾ (see Figure 6-11)

NO.			MIN	MAX	UNIT
1	t_c(SPC)S	Cycle time, SPInCLK⁽⁶⁾	100	256t_c(ICLK)	ns
2⁽⁷⁾	t_w(SPCH)S	Pulse duration, SPInCLK high (clock polarity = 0)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
2⁽⁷⁾	t_w(SPCL)S	Pulse duration, SPInCLK low (clock polarity = 1)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
3⁽⁷⁾	t_w(SPCL)S	Pulse duration, SPInCLK low (clock polarity = 0)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
3⁽⁷⁾	t_w(SPCH)S	Pulse duration, SPInCLK high (clock polarity = 1)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
4⁽⁷⁾	t_{d(SPCH-SOMI)S}	Delay time, SPInCLK high to SPInSOMI valid (clock polarity = 0)		6 + t_r
4⁽⁷⁾	t_{d(SPCL-SOMI)S}	Delay time, SPInCLK low to SPInSOMI valid (clock polarity = 1)		6 + t_f
5⁽⁷⁾	t_{v(SPCH-SOMI)S}	Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)	t_c(SPC)S – 6 – t_r
5⁽⁷⁾	t_{v(SPCL-SOMI)S}	Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)	t_c(SPC)S – 6 – t_f
6⁽⁷⁾	t_{su(SIMO-SPCL)S}	Setup time, SPInSIMO before SPInCLK low (clock polarity = 0)	6
6⁽⁷⁾	t_{su(SIMO-SPCH)S}	Setup time, SPInSIMO before SPInCLK high (clock polarity = 1)	6
7⁽⁷⁾	t_{v(SPCL-SIMO)S}	Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)	6
7⁽⁷⁾	t_{v(SPCH-SIMO)S}	Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)	6

(1) Not production tested.

(2) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(3) If the SPI is in slave mode, the following must be true: t_c(SPC)S ≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].

(4) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(5) t_c(ICLK) = interface clock cycle time = 1/ƒ_(ICLK)

(6) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)S = 2t_c(ICLK) ≥ 100 ns.

(7) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 6-11 SPIn Slave Mode External Timing (CLOCK PHASE = 0)

Table 6-13 SPIn Slave Mode External Timing Parameters⁽¹⁾

(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾ (see Figure 6-12)

NO.			MIN	MAX	UNIT
1	t_c(SPC)S	Cycle time, SPInCLK⁽⁶⁾	100	256t_c(ICLK)	ns
2⁽⁷⁾	t_w(SPCH)S	Pulse duration, SPInCLK high (clock polarity = 0)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
2⁽⁷⁾	t_w(SPCL)S	Pulse duration, SPInCLK low (clock polarity = 1)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
3⁽⁷⁾	t_w(SPCL)S	Pulse duration, SPInCLK low (clock polarity = 0)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S + 0.25t_c(ICLK)
3⁽⁷⁾	t_w(SPCH)S	Pulse duration, SPInCLK high (clock polarity = 1)	0.5t_c(SPC)S – 0.25t_c(ICLK)	0.5t_c(SPC)S+ 0.25t_c(ICLK)
4⁽⁷⁾	t_{v(SOMI-SPCH)S}	Valid time, SPInCLK high after SPInSOMI data valid (clock polarity = 0)	0.5t_c(SPC)S – 6 – t_r
4⁽⁷⁾	t_{v(SOMI-SPCL)S}	Valid time, SPInCLK low after SPInSOMI data valid (clock polarity = 1)	0.5t_c(SPC)S – 6 – t_f
5⁽⁷⁾	t_{v(SPCH-SOMI)S}	Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)	0.5t_c(SPC)S – 6 – t_r
5⁽⁷⁾	t_{v(SPCL-SOMI)S}	Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)	0.5t_c(SPC)S – 6 – t_f
6⁽⁷⁾	t_{su(SIMO-SPCH)}S	Setup time, SPInSIMO before SPInCLK high (clock polarity = 0)	6
6⁽⁷⁾	t_{su(SIMO-SPCL)}S	Setup time, SPInSIMO before SPInCLK low (clock polarity = 1)	6
7⁽⁷⁾	t_{v(SPCH-SIMO)S}	Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)	6
7⁽⁷⁾	t_{v(SPCL-SIMO)S}	Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)	6

(1) Not production tested.

(2) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(3) If the SPI is in slave mode, the following must be true: t_c(SPC) ≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].

(4) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(5) t_c(ICLK) = interface clock cycle time = 1/ƒ_(ICLK)

(7) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 6-12 SPIn Slave Mode External Timing (CLOCK PHASE = 1)

6.14 SCIN Isosynchronous Mode Timings - Internal Clock

Table 6-14 Timing Requirements for Internal Clock SCIN Isosynchronous Mode⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

(see Figure 6-13)

		(BAUD + 1) IS EVEN OR BAUD = 0		(BAUD + 1) IS ODD AND BAUD ≠ 0		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_c(SCC)	Cycle time, SCInCLK	2t_c(ICLK)	2²⁴ t_c(ICLK)	3t_c(ICLK)	(2²⁴ – 1) t_c(ICLK)	ns
t_w(SCCL)	Pulse duration, SCInCLK low	0.5t_c(SCC) – t_f	0.5t_c(SCC)+ 5	0.5t_c(SCC) + 0.5t_c(ICLK) – t_f	0.5t_c(SCC) + 0.5t_c(ICLK)	ns
t_w(SCCH)	Pulse duration, SCInCLK high	0.5t_c(SCC) – t_r	0.5t_c(SCC) + 5	0.5t_c(SCC) – 0.5t_c(ICLK) – t_r	0.5t_c(SCC) – 0.5t_c(ICLK)	ns
t_d(SCCH-TXV)	Delay time, SCInCLK high to SCInTX valid		10		10	ns
t_v(TX)	Valid time, SCInTX data after SCInCLK low	t_c(SCC) – 10		t_c(SCC) – 10		ns
t_su(RX-SCCL)	Setup time, SCInRX before SCInCLK low	t_c(ICLK) + t_f + 20		t_c(ICLK) + t_f + 20		ns
t_v(SCCL-RX)	Valid time, SCInRX data after SCInCLK low	–t_c(ICLK) + t_f + 20		–t_c(ICLK) + t_f + 20		ns

(1) Not production tested.

(2) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.

(3) t_c(ICLK) = interface clock cycle time = 1 / ƒ_(ICLK)

(4) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

NOTE:

Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge.

Figure 6-13 SCIn Isosynchronous Mode Timing Diagram for Internal Clock

6.15 SCIN Isosynchronous Mode Timings - External Clock

Table 6-15 Timing Requirements for External Clock SCIN Isosynchronous Mode⁽¹⁾⁽²⁾⁽³⁾

(see Figure 6-14)

		MIN	MAX	UNIT
t_c(SCC)	Cycle time, SCInCLK⁽⁴⁾	8t_c(ICLK)		ns
t_w(SCCH)	Pulse duration, SCInCLK high	0.5t_c(SCC) – 0.25t_c(ICLK)	0.5t_c(SCC) + 0.25t_c(ICLK)	ns
t_w(SCCL)	Pulse duration, SCInCLK low	0.5t_c(SCC) – 0.25t_c(ICLK)	0.5t_c(SCC) + 0.25t_c(ICLK)	ns
t_d(SCCH-TXV)	Delay time, SCInCLK high to SCInTX valid		2t_c(ICLK) + 12 + t_r	ns
t_v(TX)	Valid time, SCInTX data after SCInCLK low	2t_c(SCC) – 10		ns
t_su(RX-SCCL)	Setup time, SCInRX before SCInCLK low	0		ns
t_v(SCCL-RX)	Valid time, SCInRX data after SCInCLK low	2t_c(ICLK) + 10		ns

(1) Not production tested.

(2) t_c(ICLK) = interface clock cycle time = 1/ƒ_(ICLK)

(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4) When driving an external SCInCLK, the following must be true: t_c(SCC) ≥ 8t_c(ICLK).

A. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge.

Figure 6-14 SCIn Isosynchronous Mode Timing Diagram for External Clock

6.16 I²C Timing

Table 6-16 Assumes testing over recommended operating conditions.

Table 6-16 I²C Signals (SDA and SCL) Switching Characteristics⁽¹⁾⁽²⁾

PARAMETER			STANDARD MODE		FAST MODE		UNIT
PARAMETER			MIN	MAX	MIN	MAX	UNIT
t_c(I2CCLK)	Cycle time, I2C module clock		75	150	75	150	ns
t_c(SCL)	Cycle time, SCL		10		2.5		µs
t_{su(SCLH-SDAL)}	Setup time, SCL high before SDA low (for a repeated START condition)		4.7		0.6		µs
t_h(SCLL-SDAL)	Hold time, SCL low after SDA low (for a repeated START condition)		4		0.6		µs
t_w(SCLL)	Pulse duration, SCL low		4.7		1.3		µs
t_w(SCLH)	Pulse duration, SCL high		4		0.6		µs
t_su(SDA-SCLH)	Setup time, SDA valid before SCL high		250		100		ns
t_h(SDA-SCLL)	Hold time, SDA valid after SCL low	For I2C bus devices	0	3.45⁽³⁾	0	0.9	µs
t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions		4.7		1.3		µs
t_r(SCL)	Rise time, SCL			1000	20+0.1C_b⁽⁴⁾	300	ns
t_r(SDA)	Rise time, SDA			1000	20+0.1C_b⁽⁴⁾	300	ns
t_f(SCL)	Fall time, SCL			300	20+0.1C_b⁽⁴⁾	300	ns
t_f(SDA)	Fall time, SDA			300	20+0.1C_b⁽⁴⁾	300	ns
t_{su(SCLH-SDAH)}	Setup time, SCL high before SDA high (for STOP condition)		4.0		0.6		µs
t_w(SP)	Pulse duration, spike (must be suppressed)				0	50	ns
C_b⁽⁴⁾	Capacitive load for each bus line			400		400	pF

(1) Not production tested.

(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

(3) The maximum t_h(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (t_w(SCLL)) of the SCL signal.

(4) C_b = The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.

A. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

B. The maximum t_h(SDA-SCLL) needs only be met if the device does not stretch the LOW period (t_w(SCLL)) of the SCL signal.

C. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t_su(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH).

D. C_b = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.

Figure 6-15 I²C Timings

6.17 Standard Can Controller (SCC) Mode Timings

Table 6-17 Dynamic Characteristics for the CANSTX and CANSRX Pins⁽¹⁾

PARAMETER		MIN	MAX	UNIT
t_d(CANSTX)	Delay time, transmit shift register to CANSTX pin⁽²⁾		15	ns
t_d(CANSRX)	Delay time, CANSRX pin to receive shift register		5	ns

(1) Not production tested.

(2) These values do not include the rise/fall times of the output buffer.

6.18 Expansion Bus Module Timing

Table 6-18 Expansion Bus Timing Parameters⁽¹⁾

–55°C ≤ T_A ≤ 220°C, 3.0 V ≤ V _CC ≤ 3.6 V (see Figure 6-16 and Figure 6-17)

		MIN	MAX	UNIT
t_c(CO)	Cycle time, CLKOUT	20.8		ns
t_d(COH-EBADV)	Delay time, CLKOUT high to EBADDR valid		21.4	ns
t_{h(COH-EBADIV)}	Hold time, EBADDR invalid after CLKOUT high		12.4	ns
t_d(COH-EBOE)	Delay time, CLKOUT high to EBOE fall		11.4	ns
t_h(COH-EBOEH)	Hold time, EBOE rise after CLKOUT high		11.4	ns
t_d(COL-EBWR)	Delay time, CLKOUT low to write strobe (EBWR) low		11.3	ns
t_h(COL-EBWRH)	Hold time, EBWR high after CLKOUT low		11.6	ns
t_{su(EBRDATV-COH)}	Setup time, EBDATA valid before CLKOUT high (READ)⁽²⁾	15.2		ns
t_{h(COH-EBRDATIV)}	Hold time, EBDATA invalid after CLKOUT high (READ)		(–14.7)	ns
t_{d(COL-EBWDATV)}	Delay time, CLKOUT low to EBDATA valid (WRITE)⁽³⁾		16.1	ns
t_{h(COL-EBWDATIV)}	Hold time, EBDATA invalid after CLKOUT low (WRITE)		14.7	ns
SECONDARY TIMES
t_d(COH-EBCS0)	Delay, CLKOUT high to EBCS0 fall		13.6	ns
t_{h(COH-EBCS0H)}	Hold, EBCS0 rise after CLKOUT high		13.2	ns
t_{su(COH-EBHOLDL)}	Setup time, EBHOLD low to CLKOUT high⁽²⁾	10.9		ns
t_{su(COH-EBHOLDH)}	Setup time, EBHOLD high to CLKOUT high⁽²⁾	10.5		ns

(1) Not production tested.

(2) Setup time is the minimum time under worst case conditions. Data with less setup time will not work.

(3) Valid after CLKOUT goes low for write cycles.

Figure 6-16 Expansion Memory Signal Timing - Reads

Figure 6-17 Expansion Memory Signal Timing - Writes

6.19 Multi-Buffered A-to-D Converter (MibADC)

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on V SS and V CC , from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to AD REFLO unless otherwise noted.

Resolution	10 bits (1024 values)
Monotonic	Assured
Output conversion code	00h to 3FFh [00 for V_AI ≤ AD_REFLO ; 3FF for V_AI ≥ AD_REFHI ]

Table 6-19 MibADC Recommended Operating Conditions⁽¹⁾

		MIN	MAX	UNIT
AD_REFHI	A-to-D high-voltage reference source	V_SSAD	V_CCAD	V
AD_REFLO	A-to-D low-voltage reference source	V_SSAD	V_CCAD	V
V_AI	Analog input voltage	V_SSAD – 0.3	V_CCAD + 0.3	V
I_AIC	Analog input clamp current⁽²⁾ (V_AI < V_SSAD – 0.3 or V_AI > V_CCAD + 0.3)	–2	2	mA

(1) For V_CCAD and V_SSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.

(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 6-20 Operating Characteristics over Full Ranges of Recommended Operating Conditions⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

PARAMETER		DESCRIPTION/CONDITIONS		MIN	TYP	MAX	UNIT
R_I	Analog input resistance	See Figure 6-18.			250	500	Ω
C_I	Analog input capacitance	See Figure 6-18.	Conversion			10	pF
C_I	Analog input capacitance	See Figure 6-18.	Sampling			30	pF
I_AIL	Analog input leakage current	See Figure 6-18.		–1		1	µA
I_ADREFHI	AD_REFHI input current	AD_REFHI = 3.6 V, AD_REFLO = V_SSAD				5	mA
CR	Conversion range over which specified accuracy is maintained	AD_REFHI - AD_REFLO		3		3.6	V
E_DNL	Differential nonlinearity error	Difference between the actual step width and the ideal value. See Figure 6-19.				±1.5	LSB
E_INL	Integral nonlinearity error	Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. See Figure 6-20.				±2	LSB
E_TOT	Total error/Absolute accuracy	Maximum value of the difference between an analog value and the ideal midstep value. See Figure 6-21.				±2.5	LSB

(1) Not production tested.

(2) INL and DNL values are valid for a max ADCCLK frequency of 15 MHz. For frequencies greater than 15 MHz missing codes are expected at higher temperature.

(3) V_CCAD= AD_REFHI

(4) 1 LSB = (AD_REFHI - AD_REFLO)/2¹⁰ for the MibADC

Figure 6-18 MibADC Input Equivalent Circuit

Table 6-21 Multi-Buffer ADC Timing Requirements⁽¹⁾

		MIN	UNIT
t_c(ADCLK)	Cycle time, MibADC clock	0.067	µs
t_d(SH)	Delay time, sample and hold time	1	µs
t_d(c)	Delay time, conversion time	0.55	µs
t_d(SHC)⁽²⁾	Delay time, total sample/hold and conversion time	1.55	µs

(1) Not production tested.

(2) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (SPNU206).

The differential nonlinearity error shown in Figure 6-19 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB.

A. 1 LSB = (AD_REFHI – AD_REFLO) / 2¹⁰

Figure 6-19 Differential Nonlinearity (DNL)

The integral nonlinearity error shown in Figure 6-20 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line.

A. 1 LSB = (AD_REFHI – AD_REFLO) / 2¹⁰

Figure 6-20 Integral Nonlinearity (INL) Error

The absolute accuracy or total error of an MibADC as shown in Figure 6-21 is the maximum value of the difference between an analog value and the ideal midstep value.

A. 1 LSB = (AD_REFHI – AD_REFLO) / 2¹⁰

Figure 6-21 Absolute Accuracy (Total) Error

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions(1)

6.4 Electrical Characteristics

6.5 Thermal Characteristics

6.6 ZPLL and Clock Specifications

Table 6-1 Timing Requirements for ZPLL Circuits Enabled or Disabled(1)

Table 6-2 Switching Characteristics over Recommended Operating Conditions for Clocks(1)(2)(3)(4)

Table 6-3 Switching Characteristics over Recommended Operating Conditions for External Clocks(1)(2)(3)(4)

6.7 RST and PORRST Timings

Table 6-4 Timing Requirements for PORRST(1)

Table 6-5 Switching Characteristics over Recommended Operating Conditions for RST(1)(2)

6.8 JTAG Scan Interface Timing

Table 6-6 JTAG Clock Specification 10-MHz and 50-pF Load on TDO Output(1)

6.9 Output Timings

Table 6-7 Switching Characteristics for Output Timings versus Load Capacitance (CL)(1)

6.10 Input Timings

Table 6-8 Timing Requirements for Input Timings(1)(2)

6.11 Flash Timings

Table 6-9 Timing Requirements for Program Flash(1)(2)

6.12 SPIn Master Mode Timing Parameters

Table 6-10 SPIn Master Mode External Timing Parameters

Table 6-11 SPIn Master Mode External Timing Parameters(1)

6.13 SPIn Slave Mode Timing Parameters

Table 6-12 SPIn Slave Mode External Timing Parameters(1)

Table 6-13 SPIn Slave Mode External Timing Parameters(1)

6.14 SCIN Isosynchronous Mode Timings - Internal Clock

Table 6-14 Timing Requirements for Internal Clock SCIN Isosynchronous Mode(1)(2)(3)(4)

6.15 SCIN Isosynchronous Mode Timings - External Clock

Table 6-15 Timing Requirements for External Clock SCIN Isosynchronous Mode(1)(2)(3)

6.16 I2C Timing

Table 6-16 I2C Signals (SDA and SCL) Switching Characteristics(1)(2)

6.17 Standard Can Controller (SCC) Mode Timings

Table 6-17 Dynamic Characteristics for the CANSTX and CANSRX Pins(1)

6.18 Expansion Bus Module Timing

Table 6-18 Expansion Bus Timing Parameters(1)

6.19 Multi-Buffered A-to-D Converter (MibADC)

Table 6-19 MibADC Recommended Operating Conditions(1)

Table 6-20 Operating Characteristics over Full Ranges of Recommended Operating Conditions(1)(2)(3)(4)

Table 6-21 Multi-Buffer ADC Timing Requirements(1)

6.3 Recommended Operating Conditions⁽¹⁾

Table 6-1 Timing Requirements for ZPLL Circuits Enabled or Disabled⁽¹⁾

Table 6-2 Switching Characteristics over Recommended Operating Conditions for Clocks⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

Table 6-3 Switching Characteristics over Recommended Operating Conditions for External Clocks⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

Table 6-4 Timing Requirements for PORRST⁽¹⁾

Table 6-5 Switching Characteristics over Recommended Operating Conditions for RST⁽¹⁾⁽²⁾

Table 6-6 JTAG Clock Specification 10-MHz and 50-pF Load on TDO Output⁽¹⁾

Table 6-7 Switching Characteristics for Output Timings versus Load Capacitance (C_L)⁽¹⁾

Table 6-8 Timing Requirements for Input Timings⁽¹⁾⁽²⁾

Table 6-9 Timing Requirements for Program Flash⁽¹⁾⁽²⁾

Table 6-11 SPIn Master Mode External Timing Parameters⁽¹⁾

Table 6-12 SPIn Slave Mode External Timing Parameters⁽¹⁾

Table 6-13 SPIn Slave Mode External Timing Parameters⁽¹⁾

Table 6-14 Timing Requirements for Internal Clock SCIN Isosynchronous Mode⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

Table 6-15 Timing Requirements for External Clock SCIN Isosynchronous Mode⁽¹⁾⁽²⁾⁽³⁾

6.16 I²C Timing

Table 6-16 I²C Signals (SDA and SCL) Switching Characteristics⁽¹⁾⁽²⁾

Table 6-17 Dynamic Characteristics for the CANSTX and CANSRX Pins⁽¹⁾

Table 6-18 Expansion Bus Timing Parameters⁽¹⁾

Table 6-19 MibADC Recommended Operating Conditions⁽¹⁾

Table 6-20 Operating Characteristics over Full Ranges of Recommended Operating Conditions⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

Table 6-21 Multi-Buffer ADC Timing Requirements⁽¹⁾