SGUS033A February   2002  – May 2016 SMJ320C6203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Characteristics of the C6203 DSP
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Timing Requirements for CLKIN (PLL Used)
    6. 7.6  Timing Requirements for CLKIN [PLL Bypassed (x1)]
    7. 7.7  Timing Requirements for XCLKIN
    8. 7.8  Timing Requirements for Asynchronous Memory Cycles
    9. 7.9  Timing Requirements for Synchronous-Burst SRAM Cycles
    10. 7.10 Timing Requirements for Synchronous DRAM Cycles
    11. 7.11 Timing Requirements for the HOLD/HOLDA Cycles
    12. 7.12 Timing Requirements for Reset
    13. 7.13 Timing Requirements for Interrupt Response Cycles
    14. 7.14 Timing Requirements for Synchronous FIFO Interface
    15. 7.15 Timing Requirements for Asynchronous Peripheral Cycles
    16. 7.16 Timing Requirements With External Device as Bus Master
    17. 7.17 Timing Requirements With C62x as Bus Master
    18. 7.18 Timing Requirements With External Device as Asynchronous Bus Master
    19. 7.19 Timing Requirements for Expansion Bus Arbitration (Internal Arbiter Enabled)
    20. 7.20 Timing Requirements for McBSP
    21. 7.21 Timing Requirements for FSR when GSYNC = 1
    22. 7.22 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
    23. 7.23 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    24. 7.24 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    25. 7.25 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    26. 7.26 Timing Requirements for Timer Inputs
    27. 7.27 Timing Requirements for JTAG Test Port
    28. 7.28 Switching Characteristics for CLKOUT2
    29. 7.29 Switching Characteristics for XFCLK
    30. 7.30 Asynchronous Memory Timing Switching Characteristics
    31. 7.31 Switching Characteristics for Synchronous-Burst SRAM Cycles
    32. 7.32 Switching Characteristics for Synchronous DRAM Cycles
    33. 7.33 Switching Characteristics for the HOLD/HOLDA Cycles
    34. 7.34 Switching Characteristics for Reset
    35. 7.35 Switching Characteristics for Interrupt Response Cycles
    36. 7.36 Switching Characteristics for Synchronous FIFO Interface
    37. 7.37 Switching Characteristics for Asynchronous Peripheral Cycles
    38. 7.38 Switching Characteristics With External Device as Bus Master
    39. 7.39 Switching Characteristics With C62x as Bus Master
    40. 7.40 Switching Characteristics With External Device as Asynchronous Bus Master
    41. 7.41 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Enabled)
    42. 7.42 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Disabled)
    43. 7.43 Switching Characteristics for McBSP
    44. 7.44 Switching Characteristics for McBSP as SPI Master or Slave
    45. 7.45 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    46. 7.46 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    47. 7.47 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    48. 7.48 Switching Characteristics for DMAC Outputs
    49. 7.49 Switching Characteristics for Timer Outputs
    50. 7.50 Switching Characteristics for Power-Down Outputs
    51. 7.51 Switching Characteristics for JTAG Test Port
  8. 8 Parameter Measurement Information
    1. 8.1 Signal Transition Levels
    2. 8.2 Timing Parameters and Board Routing Analysis
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Signal Groups Description
      2. 9.2.2 CPU (DSP Core) Description
      3. 9.2.3 Clock PLL
    3. 9.3 Register Maps
      1. 9.3.1 Memory Map Summary
      2. 9.3.2 Peripheral Register Descriptions
      3. 9.3.3 Interrupt Sources and Interrupt Selector
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 System-Level Design Considerations
    3. 11.3 Power-Supply Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Software Development Tools
        2. 12.1.2.2 Hardware Development Tools
      3. 12.1.3 Device and Development-Support Tool Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • GLP|429
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

SMJ320C6203 pmi_gus033.gif
Where: IOL = 2 mA, IOH = 2 mA, Vcomm = 2.1 V, CT = 15-pF typical load-circuit capacitance
Figure 1. Test Load Circuit for AC Timing Measurements

8.1 Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.

SMJ320C6203 tim_ac_gus033.gif Figure 2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks.

SMJ320C6203 tim_rise_fall_gus033.gif Figure 3. Rise and Fall Transition Time Voltage Reference Levels

8.2 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, always account for such delays. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 1 and Figure 4).

Figure 4 represents a general transfer between the DSP and an external device. Figure 4 also represents board route delays and how they are perceived by the DSP and the external device.

Table 1. IBIS Timing Parameters Example (See Figure 4)

NO. DESCRIPTION
1 Clock route delay
2 Minimum DSP hold time
3 Minimum DSP setup time
4 External device hold time requirement
5 External device setup time requirement
6 Control signal route delay
7 External device hold time
8 External device access time
9 DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
SMJ320C6203 tim_IBIS_gus033.gif
  1. Control signals include data for Writes.
  2. Data signals are generated during Reads from an external device.
Figure 4. IBIS Input/Output Timings
SMJ320C6203 tim_CLKIN_gus033.gif Figure 5. CLKIN Timings
SMJ320C6203 tim_XCLKIN_gus033.gif Figure 6. XCLKIN Timings
SMJ320C6203 tim_CLCKOUT2_gus033.gif Figure 7. CLKOUT2 Timings
SMJ320C6203 tim_XFCLK_gus033.gif Figure 8. XFCLK Timings
SMJ320C6203 tim_asynch_r_ARDY_not_gus033.gif
  1. CEx stays active for 7 – the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the overhead of the EMIF.
Figure 9. Asynchronous Memory Read Timing (ARDY Not Used)
SMJ320C6203 tim_asynch_r_ARDY_used_gus033.gif
  1. CEx stays active for 7 – the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the overhead of the EMIF.
Figure 10. Asynchronous Memory Read Timing (ARDY Used)
SMJ320C6203 tim_asynch_w_ARDY_not_gus033.gif
  1. If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely reflects the overhead of the EMIF.
Figure 11. Asynchronous Memory Write Timing (ARDY Not Used)
SMJ320C6203 tim_asynch_w_ARDY_used_gus033.gif
  1. If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely reflects the overhead of the EMIF.
Figure 12. Asynchronous Memory Write Timing (ARDY Used)
SMJ320C6203 tim_SBSRAM_r_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 13. SBSRAM Read Timing
SMJ320C6203 tim_SBSRAM_w_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 14. SBSRAM Write Timing
SMJ320C6203 tim_SDRAM_r_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 15. Three SDRAM READ Commands
SMJ320C6203 tim_SDRAM_w_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 16. Three SDRAM WRT Commands
SMJ320C6203 tim_SDRAM_ACTV_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 17. SDRAM ACTV Command
SMJ320C6203 tim_SDRAM_DCAB_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 18. SDRAM DCAB Command
SMJ320C6203 tim_SDRAM_REFR_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 19. SDRAM REFR Command
SMJ320C6203 tim_SDRAM_MRS_gus033.gif
  1. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 20. SDRAM MRS Command
SMJ320C6203 tim_HOLD_A_gus033.gif
  1. EMIF bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 21. HOLD/HOLDA Timing
SMJ320C6203 tim_reset_gus033.gif
  1. High group consists of: XFCLK, HOLDA
  2. Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
  3. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA
  4. XD[31:0] are the boot configuration pins during device reset.
Figure 22. Reset Timing
SMJ320C6203 tim_interupt_gus033.gif Figure 23. Interrupt Timing
SMJ320C6203 tim_FIFO_r_glueless_gus033.gif
  1. FIFO read (glueless) mode only available in XCE3.
  2. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
  3. XWE/XWAIT operate as the write-enable signal XWE during synchronous FIFO accesses.
Figure 24. FIFO Read Timing (Glueless Read Mode)
SMJ320C6203 tim_FIFO_r_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
  2. XWE/XWAIT operate as the write-enable signal XWE during synchronous FIFO accesses.
Figure 25. FIFO Read Timing
SMJ320C6203 tim_FIFO_w_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
  2. XWE/XWAIT operate as the write-enable signal XWE during synchronous FIFO accesses.
Figure 26. FIFO Write Timing
SMJ320C6203 tim_exp_bus_XRDY_not_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
  2. XWE/XWAIT operate as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
  3. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 27. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)
SMJ320C6203 tim_exp_bus_XRDY_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
  2. XWE/XWAIT operate as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
  3. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 28. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)
SMJ320C6203 tim_exp_bus_w_XRDY_not_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
  2. XWE/XWAIT operate as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
  3. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 29. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)
SMJ320C6203 tim_exp_bus_w_XRDY_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
  2. XWE/XWAIT operate as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
  3. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 30. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)
SMJ320C6203 tim_host_r_gus033.gif
  1. XW/R input/output polarity selected at boot
  2. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  3. XBLAST input polarity selected at boot
  4. XRDY operates as active-low ready input/output during host-port accesses.
Figure 31. External Host as Bus Master—Read
SMJ320C6203 tim_host_w_gus033.gif
  1. XW/R input/output polarity selected at boot
  2. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  3. XBLAST input polarity selected at boot
  4. XRDY operates as active-low ready input/output during host-port accesses.
Figure 32. External Host as Bus Master—Write
SMJ320C6203 tim_bus_r_gus033.gif
  1. XW/R input/output polarity selected at boot
  2. XBLAST output polarity is always active low.
  3. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  4. XWE/XWAIT operate as XWAIT output signal during host-port accesses.
Figure 33. C62x as Bus Master—Read
SMJ320C6203 tim_bus_w_gus033.gif
  1. XW/R input/output polarity selected at boot
  2. XBLAST output polarity is always active low.
  3. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  4. XWE/XWAIT operate as XWAIT output signal during host-port accesses.
Figure 34. C62x as Bus Master—Write
SMJ320C6203 tim_BOFF_op_gus033.gif
  1. XW/R input/output polarity selected at boot
  2. XBLAST output polarity is always active low.
  3. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  4. Internal arbiter enabled
  5. External arbiter enabled

NOTE:

This diagram illustrates XBOFF timing. Figure 38 and Figure 39 show bus arbitration timing.
Figure 35. C62x as Bus Master—BOFF Operation
SMJ320C6203 tim_ext_dev_r_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  2. XW/R input/output polarity selected at boot
Figure 36. External Device as Asynchronous Master—Read
SMJ320C6203 tim_ext_dev_w_gus033.gif
  1. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
  2. XW/R input/output polarity selected at boot
Figure 37. External Device as Asynchronous Master—Write
SMJ320C6203 tim_int_arb_en_gus033.gif
  1. Expansion bus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 38. Expansion Bus Arbitration—Internal Arbiter Enabled
SMJ320C6203 tim_int_arb_dis_gus033.gif
  1. Expansion bus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled
SMJ320C6203 tim_McBSP_gus033.gif Figure 40. McBSP Timings
SMJ320C6203 tim_FSR_gus033.gif Figure 41. FSR Timing When GSYNC = 1
SMJ320C6203 tim_McBSP_10b_gus033.gif Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
SMJ320C6203 tim_McBSP_11b_gus033.gif Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
SMJ320C6203 tim_McBSP_10b_1_gus033.gif Figure 44. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
SMJ320C6203 tim_McBSP_11b_1_gus033.gif Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
SMJ320C6203 tim_DMAC_gus033.gif Figure 46. DMAC Timing
SMJ320C6203 tim_timer_gus033.gif Figure 47. Timer Timing
SMJ320C6203 tim_pwr_down_gus033.gif Figure 48. Power-Down Timing
SMJ320C6203 tim_JTAG_gus033.gif Figure 49. JTAG Test-Port Timing