SGUS033A February   2002  – May 2016 SMJ320C6203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Characteristics of the C6203 DSP
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Timing Requirements for CLKIN (PLL Used)
    6. 7.6  Timing Requirements for CLKIN [PLL Bypassed (x1)]
    7. 7.7  Timing Requirements for XCLKIN
    8. 7.8  Timing Requirements for Asynchronous Memory Cycles
    9. 7.9  Timing Requirements for Synchronous-Burst SRAM Cycles
    10. 7.10 Timing Requirements for Synchronous DRAM Cycles
    11. 7.11 Timing Requirements for the HOLD/HOLDA Cycles
    12. 7.12 Timing Requirements for Reset
    13. 7.13 Timing Requirements for Interrupt Response Cycles
    14. 7.14 Timing Requirements for Synchronous FIFO Interface
    15. 7.15 Timing Requirements for Asynchronous Peripheral Cycles
    16. 7.16 Timing Requirements With External Device as Bus Master
    17. 7.17 Timing Requirements With C62x as Bus Master
    18. 7.18 Timing Requirements With External Device as Asynchronous Bus Master
    19. 7.19 Timing Requirements for Expansion Bus Arbitration (Internal Arbiter Enabled)
    20. 7.20 Timing Requirements for McBSP
    21. 7.21 Timing Requirements for FSR when GSYNC = 1
    22. 7.22 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
    23. 7.23 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    24. 7.24 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    25. 7.25 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    26. 7.26 Timing Requirements for Timer Inputs
    27. 7.27 Timing Requirements for JTAG Test Port
    28. 7.28 Switching Characteristics for CLKOUT2
    29. 7.29 Switching Characteristics for XFCLK
    30. 7.30 Asynchronous Memory Timing Switching Characteristics
    31. 7.31 Switching Characteristics for Synchronous-Burst SRAM Cycles
    32. 7.32 Switching Characteristics for Synchronous DRAM Cycles
    33. 7.33 Switching Characteristics for the HOLD/HOLDA Cycles
    34. 7.34 Switching Characteristics for Reset
    35. 7.35 Switching Characteristics for Interrupt Response Cycles
    36. 7.36 Switching Characteristics for Synchronous FIFO Interface
    37. 7.37 Switching Characteristics for Asynchronous Peripheral Cycles
    38. 7.38 Switching Characteristics With External Device as Bus Master
    39. 7.39 Switching Characteristics With C62x as Bus Master
    40. 7.40 Switching Characteristics With External Device as Asynchronous Bus Master
    41. 7.41 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Enabled)
    42. 7.42 Switching Characteristics for Expansion Bus Arbitration (Internal Arbiter Disabled)
    43. 7.43 Switching Characteristics for McBSP
    44. 7.44 Switching Characteristics for McBSP as SPI Master or Slave
    45. 7.45 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
    46. 7.46 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
    47. 7.47 Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
    48. 7.48 Switching Characteristics for DMAC Outputs
    49. 7.49 Switching Characteristics for Timer Outputs
    50. 7.50 Switching Characteristics for Power-Down Outputs
    51. 7.51 Switching Characteristics for JTAG Test Port
  8. 8 Parameter Measurement Information
    1. 8.1 Signal Transition Levels
    2. 8.2 Timing Parameters and Board Routing Analysis
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Signal Groups Description
      2. 9.2.2 CPU (DSP Core) Description
      3. 9.2.3 Clock PLL
    3. 9.3 Register Maps
      1. 9.3.1 Memory Map Summary
      2. 9.3.2 Peripheral Register Descriptions
      3. 9.3.3 Interrupt Sources and Interrupt Selector
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 System-Level Design Considerations
    3. 11.3 Power-Supply Design Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Software Development Tools
        2. 12.1.2.2 Hardware Development Tools
      3. 12.1.3 Device and Development-Support Tool Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • GLP|429
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GLP Package
429-Pin CFCBGA
Bottom View
SMJ320C6203 po_gus033.gif

Signal Descriptions

SIGNAL NAME PIN NO. TYPE(1) DESCRIPTION
CLOCK/PLL
CLKIN D10 I Clock input
CLKOUT1 Y17 O Clock output at full device speed
CLKOUT2 Y16 O Clock output at half of device speed; used for synchronous memory interface
CLKMODE0 C12 I Clock mode selects; selects what multiply factors of the input clock frequency the CPU frequency equals.
For more details on the CLKMODE pins and the PLL multiply factors for the C6203 device, see Clock PLL
CLKMODE1 G10 I
CLKMODE2 G12 I
PLLV(2) B11 A(3) PLL analog VCC connection for the low-pass filter
PLLG(2) A11 A(3) PLL analog GND connection for the low-pass filter
PLLF(2) G11 A(3) PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS W5 I JTAG test-port mode select (features an internal pullup)
TDO R8 O/Z JTAG test-port data out
TDI W4 I JTAG test-port data in (features an internal pullup)
TCK V5 I JTAG test-port clock
TRST R7 I JTAG test-port reset (features an internal pulldown)
EMU1 T7 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor
EMU0 Y5 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor
RESET AND INTERRUPTS
RESET J4 I Device reset
NMI K2 I Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7 R4 I External interrupts
  • Edge-driven
  • Polarity independently selected via the External Interrupt Polarity register bits (EXTPOL.[3:0])
EXT_INT6 P6
EXT_INT5 T2
EXT_INT4 T3
IACK R2 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 P4 O Active interrupt identification number
  • Valid during IACK for all active interrupts (not just external)
  • Encoding order follows the interrupt-service fetch-packet ordering
INUM2 P1
INUM1 P2
INUM0 N6
POWER-DOWN STATUS
PD V3 O Power-down modes 2 or 3 (active if high)
EXPANSION BUS
XCLKIN C9 I Expansion bus synchronous host interface clock input
XFCLK B9 O Expansion bus FIFO interface clock output
XD31 D11 I/O/Z Expansion bus data
  • Used for transfer of data, address, and control
  • Also controls initialization of DSP modes and expansion bus at reset

Note: For more information on pin control and boot configuration fields, see TMS320C6000 Peripherals Reference Guide (SPRU190)
XD[30:16] − XCE[3:0] memory type
XD13 − XBLAST polarity
XD12 − XW/R polarity
XD11 − Asynchronous or synchronous host operation
XD10 − Arbitration mode (internal or external) XD9 − FIFO mode
XD8 − Little endian/big endian
XD7 − SCRT select
XD[4:0] − Boot mode
All other expansion bus data pins not listed should be pulled down.
For proper operation, XD7 must be pulled down with a 10-kΩ resistor. The board design should be wired such that a pullup or pulldown resistor can be used on XD7 for future applications.
XD30 B13
XD29 F12
XD28 C13
XD27 D12
XD26 A14
XD25 B14
XD24 F13
XD23 B15
XD22 C15
XD21 D13
XD20 B16
XD19 B17
XD18 D14
XD17 F15
XD16 C17
XD15 G14
XD14 D17
XD13 C18
XD12 E18
XD11 D18
XD10 G15
XD9 D19
XD8 F16
XD7 F19
XD6 E20
XD5 G16
XD4 H19
XD3 G20
XD2 J18
XD1 H20
XD0 H21
XCE3 D3 O/Z Expansion bus I/O port memory space enables
  • Enabled by bits 28, 29, and 30 of the word address
  • Only one asserted during any I/O port data access
XCE2 G6
XCE1 D4
XCE0 E4
XBE3/XA5 F6 I/O/Z Expansion bus multiplexed byte-enable control/address signals
  • Act as byte-enable for host-port operation
  • Act as address for I/O port operation
XBE2/XA4 F7
XBE1/XA3 B5
XBE0/XA2 C7
XOE B7 O/Z Expansion bus I/O port output-enable
XRE B8 O/Z Expansion bus I/O port read-enable
XWE/XWAIT D7 O/Z Expansion bus I/O port write-enable and host-port wait signals
XCS D8 I Expansion bus host-port chip-select input
XAS G9 I/O/Z Expansion bus host-port address strobe
XCNTL A9 I Expansion bus host control. XCNTL selects between expansion bus address or data register.
XW/R F9 I/O/Z Expansion bus host-port write/read-enable. XW/R polarity is selected at reset.
XRDY F4 I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high)
XBLAST C5 I/O/Z Expansion bus host-port burst last-polarity selected at reset
XBOFF C10 I Expansion bus back off
XHOLD C4 I/O/Z Expansion bus hold request
XHOLDA D6 I/O/Z Expansion bus hold acknowledge
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 V18 O/Z Memory space enables
  • Enabled by bits 24 and 25 of the word address
  • Only one asserted during any external data access
CE2 W18
CE1 T15
CE0 U18
BE3 R15 O/Z Byte-enable control
  • Decoded from the two lowest bits of the internal address
  • Byte-write enables for most types of memory
  • Can be directly connected to SDRAM read and write mask signal (SDQM)
BE2 V19
BE1 U20
BE0 V16
EMIF − ADDRESS
EA21 K18 O/Z External address (word address)
EA20 K16
EA19 J20
EA18 K19
EA17 J21
EA16 K20
EA15 M19
EA14 L16
EA13 K21
EA12 M18
EA11 L21
EA10 N18
EA9 M20
EA8 M16
EA7 R18
EA6 M21
EA5 N21
EA4 N16
EA3 P20
EA2 T18
EMIF − DATA
ED31 V6 I/O/Z External data
ED30 Y6
ED29 T8
ED28 Y7
ED27 Y8
ED26 V7
ED25 T9
ED24 AA8
ED23 V8
ED22 Y9
ED21 AA9
ED20 V9
ED19 T10
ED18 Y10
ED17 W9
ED16 V10
ED15 T11
ED14 AA10
ED13 W10
ED12 W12
ED11 Y11
ED10 Y12
ED9 T12
ED8 AA13
ED7 R12
ED6 V13
ED5 Y13
ED4 Y14 I/O/Z External data
ED3 T13
ED2 Y15
ED1 R13
ED0 V14
EMIF − ASYNCHRONOUS MEMORY CONTROL
ARE T20 O/Z Asynchronous memory read-enable
AOE P16 O/Z Asynchronous memory output-enable
AWE R20 O/Z Asynchronous memory write-enable
ARDY R16 I Asynchronous memory ready input
EMIF − SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10 T14 O/Z SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS V17 O/Z SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE W17 O/Z SDRAM row-address strobe/SBSRAM output-enable
SDWE/SSWE W15 O/Z SDRAM write-enable/SBSRAM write-enable
EMIF − BUS ARBITRATION
HOLD T19 I Hold request from the host
HOLDA T16 O Hold-request-acknowledge to the host
TIMER 0
TOUT0 F2 O Timer 0 or general-purpose output
TINP0 E2 I Timer 0 or general-purpose input
TIMER 1
TOUT1 G4 O Timer 1 or general-purpose output
TINP1 H6 I Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3 R6 O DMA action complete
DMAC2 U2
DMAC1 T6
DMAC0 V4
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 K6 I External clock source (as opposed to internal)
CLKR0 L1 I/O/Z Receive clock
CLKX0 K3 I/O/Z Transmit clock
DR0 M1 I Receive data
DX0 L6 O/Z Transmit data
FSR0 L2 I/O/Z Receive frame sync
FSX0 L3 I/O/Z Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 G2 I External clock source (as opposed to internal)
CLKR1 H2 I/O/Z Receive clock
CLKX1 H4 I/O/Z Transmit clock
DR1 J2 I Receive data
DX1 H3 O/Z Transmit data
FSR1 J6 I/O/Z Receive frame sync
FSX1 J1 I/O/Z Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
CLKS2 L4 I External clock source (as opposed to internal)
CLKR2 M2 I/O/Z Receive clock
CLKX2 N4 I/O/Z Transmit clock
DR2 P3 I Receive data
DX2 N2 O/Z Transmit data
FSR2 M6 I/O/Z Receive frame sync
FSX2 N1 I/O/Z Transmit frame sync
RESERVED FOR TEST
RSV0 K1 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1 F3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2 A10 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3 F11 O Reserved (leave unconnected, do not connect to power or ground)
RSV4 D9 O Reserved (leave unconnected, do not connect to power or ground)
N/C R11 — No connect
R9 —
W7 —
SUPPLY VOLTAGE PINS
DVDD - 3.3 V C8, C14, E3 , E19, H9 , H11, H13, J3, J8, J10, J12, J14, J19, K7, K9, K11, K13, K15, L8, L10, L12, L14, M7, M9, M11, M13, M15, N3, N8, N10, N12, N14, N19, P9, P11, P13, U3, U19, W8, W14, A3, A5, A7, A12, A13, A16, A18, B2, B4, B6, B10, B12, B19, C1, C3, C20, D2, D15, D16, D21, E1, E6, E8, E10, E12, E14, E16 S 3.3-V supply voltage (I/O)
CVDD - 1.5 V F5, F8, F10, F14, F17, F20, F21, G1, G7, G8, G13, G18, H5, H16, H17, H18, K4, K5, K17, L18, L19, L20, M3, M4, M5, M17, N20, P5, P17, P18, P19, R10, R14, R21, T1, T5, T17, U4, U6, U8, U10, U12, U14, U16, U21, V1, V11, V12, V15, V20, W2, W13, W19, W21, Y3, Y18, Y20, AA4, AA6, AA11, AA12, AA15, AA17, AA19 S 1.5-V supply voltage (core)
GROUND PINS
VSS A4, A6, A8, A15, A17, A19, B3, B18, B20, C2, C6, C11, C16, C19, C21, D1, D5, D20, E5, E7, E9, E11, E13, E15, E17, E21, F1, F18, G3, G5, G17, G19, G21, H1, H7, H8, H10, H12, H14, H15, J5, J7, J9, J11, J13, J15, J16, J17, K8, K10, K12, K14, L5, L7, L9, L11, L13, L15, L17, M8, M10, M12, M14, N5, N7, N9, N11, N13, N15, N17, P7, P8, P10, P12, P14, P15, P21, R1, R3, R5, R17, R19, T4, T21, U1, U5, U7, U9, U11, U13, U15, U17, V2, V21, W1, W3, W6, W11, W16, W20, Y2, Y4, Y19, AA3, AA5, AA7, AA14, AA16, AA18 GND Ground pins
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
(2) PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See Clock PLL for information on how to connect these pins.
(3) A = Analog signal (PLL filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor.