SGUS034F February   2001  – June 2015 SMJ320VC33

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Electrical Characteristics
    4. 6.4  Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements
    5. 6.5  Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements
    6. 6.6  Timing Requirements for EXTCLK, All Modes
    7. 6.7  Timing Requirements for Memory Read/Write for STRB
    8. 6.8  Timing Requirements for XF0 and XF1 when Executing LDFI or LDII
    9. 6.9  Timing Requirements for XF0 and XF1 when Executing SIGI
    10. 6.10 Timing Requirements for Changing XFx from Output to Input Mode
    11. 6.11 Timing Requirements for RESET
    12. 6.12 Timing Requirements for INT3 to INT0 Response
    13. 6.13 Timing Requirements for Serial Port
    14. 6.14 Timing Requirements for HOLD/HOLDA
    15. 6.15 Timing Requirements for Peripheral Pin General-Purpose I/O
    16. 6.16 Timing Requirements for Timer Pin
    17. 6.17 Timing Requirements for IEEE-1149.1 Test Access Port
    18. 6.18 Switching Characteristics for EXTCLK, All Modes
    19. 6.19 Switching Characteristics for Memory Read/Write for STRB
    20. 6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII
    21. 6.21 Switching Characteristics for XF0 when Executing STFI or STII
    22. 6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI
    23. 6.23 Switching Characteristics for Loading when XF is Configured as an Output
    24. 6.24 Switching Characteristics for Changing XFx from Output to Input Mode
    25. 6.25 Switching Characteristics for Changing XFx from an Input to an Output
    26. 6.26 Switching Characteristics for RESET
    27. 6.27 Switching Characteristics for IACK
    28. 6.28 Switching Characteristics for Serial Port
    29. 6.29 Switching Characteristics for HOLD/HOLDA
    30. 6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O
    31. 6.31 Switching Characteristics for Timer Pin
    32. 6.32 Switching Characteristics for SHZ
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  JTAG Scan-Based Emulation Logic
      2. 8.2.2  Clock Generator
      3. 8.2.3  PLL and Clock Oscillator Control
      4. 8.2.4  PLL Isolation
      5. 8.2.5  Clock and PLL Considerations on Initialization
      6. 8.2.6  EDGEMODE
      7. 8.2.7  Reset Operation
      8. 8.2.8  PAGE0 to PAGE3 Select Lines
      9. 8.2.9  Using External Logic With the READY Pin
      10. 8.2.10 Posted Writes
      11. 8.2.11 Data Bus I/O Buffer
      12. 8.2.12 Bootloader Operation
      13. 8.2.13 JTAG Emulation
      14. 8.2.14 Designing a Target System Emulator Connector (14-Pin Header)
      15. 8.2.15 JTAG Emulator Cable Pod Logic
      16. 8.2.16 Reset Timing
      17. 8.2.17 Interrupt Response TIming
      18. 8.2.18 Interrupt-Acknowledge Timing
      19. 8.2.19 Data-Rate Timing Modes
      20. 8.2.20 HOLD Timing
      21. 8.2.21 General-Purpose I/O Timing
      22. 8.2.22 Peripheral Pin I/O Timing
      23. 8.2.23 Timer Pin Timing
    3. 8.3 Register Maps
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing Considerations
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Timing Parameter Symbology
      2. 10.2.2 Device and Development-Support Tool Nomenclature
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFG|164
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

SM320VC33 SMJ320VC33 test_load_circuit_SGUS034.gif

WHERE:

  • IOL = 4 mA (all outputs) for dc levels test.
  • IO and IOH are adjusted during ac timing analysis to achieve an ac termination of 50 Ω
  • VLOAD = DVDD / 2
  • CT = 40-pF typical load-circuit capacitance
Figure 1. Test Load Circuit
SM320VC33 SMJ320VC33 on_chip_oscill_cir_SGUS034.gif
1. See Table 3 for value of Rd.
Figure 2. On-Chip Oscillator Circuit
SM320VC33 SMJ320VC33 div_by_two_mode_SGUS034.gifFigure 3. Divide-by-Two Mode
SM320VC33 SMJ320VC33 div_by_one_mode_SGUS034.gif
EXTCLK is held low.
Figure 4. Divide-by-One Mode
SM320VC33 SMJ320VC33 output_load_charact_buf_only_SGUS034.gif
This figure shows output load characteristics for high-speed and low-speed (low-noise) output buffers. High-speed buffers are used on A0 to A23, PAGE0 to PAGE3, H1, H3, STRB, and R/W. All other outputs use the low-speed, (low-noise) output buffer.
CLmax = 30 pF
Figure 5. Output Load Characteristics, Buffer Only
SM320VC33 SMJ320VC33 timg_for_memory_read_SGUS034.gif
STRB remains low during back-to-back read operations.
Figure 6. Timing for Memory (STRB = 0 and PAGEx = 0) Read
SM320VC33 SMJ320VC33 timg_for_memory_write_SGUS034.gifFigure 7. Timing for Memory (STRB = 0 and PAGEx = 0) Write
SM320VC33 SMJ320VC33 timg_for_XF0_XF1_SGUS034.gifFigure 8. Timing for XF0 and XF1 When Executing LDFI or LDII
SM320VC33 SMJ320VC33 timg_for_XF0_SGUS034.gifFigure 9. Timing for XF0 When Executing an STFI or STII
SM320VC33 SMJ320VC33 timg_for_XF0_XF1_w_SIGI_SGUS034.gifFigure 10. Timing for XF0 and XF1 When Executing SIGI
SM320VC33 SMJ320VC33 timg_for_loadg_XF_register_SGUS034.gif
  1. OUTXFx represents either bit 2 or 6 of the IOF register
.
Figure 11. Timing for Loading XF Register When Configured as an Output Pin
SM320VC33 SMJ320VC33 timg_for_changing_XFx_out_in_SGUS034.gif
  1. I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 12. Timing for Changing XFx from Output to Input Mode
SM320VC33 SMJ320VC33 timg_for_changing_XFx_in_out_SGUS034.gif
  1. I/OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 13. Timing for Changing XFx from Input to Output Mode
SM320VC33 SMJ320VC33 reset_timing_SGUS034.gif
  1. Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3.
  2. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
  3. RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the reset vector is fetched twice, with no software wait states.
The address and PAGE3 to PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10- to 22-kΩ pullup. If not, undesirable spurious reads can occur when these outputs are not driven.
Figure 14. RESET Timing
SM320VC33 SMJ320VC33 INT3_INT0_response_timg_SGUS034.gif
  1. Falling edge of H1 just detects INTx falling edge.
  2. Falling edge of H1 detects second INTx low, however flag clear takes precedence.
  3. Nominal width
  4. Falling edge of H1 misses previous INTx low as INTx rises.
Figure 15. INT3 to INT0 Response Timing
SM320VC33 SMJ320VC33 interupt_acknow_IACK_SGUS034.gifFigure 16. Interrupt Acknowledge (IACK) Timing
SM320VC33 SMJ320VC33 timg_HOLD__after_write_SGUS034.gif
HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.
Figure 17. Timing for HOLD/HOLDA (After Write)
SM320VC33 SMJ320VC33 timg_HOLD__after_read_SGUS034.gif
HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.
Figure 18. Timing for HOLD/HOLDA (After Read)
SM320VC33 SMJ320VC33 chg_periph_pin_out_in_mode_SGUS034.gif
  1. Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 19. Change of Peripheral Pin from General-Purpose Output to Input Mode Timing
SM320VC33 SMJ320VC33 chg_periph_pin_in_out_mode_SGUS034.gif
  1. Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 20. Change of Peripheral Pin from General-Purpose Input to Output Mode Timing
SM320VC33 SMJ320VC33 timer_pin_timing_input_SGUS034.gifFigure 21. Timer Pin Timing, Input
SM320VC33 SMJ320VC33 timer_pin_timing_output_SGUS034.gifFigure 22. Timer Pin Timing, Output
SM320VC33 SMJ320VC33 timing_for_SHZ_SGUS034.gif
Enabling SHZ destroys SMx320VC33 register and memory contents. Assert SHZ = 1 and reset the SMx320VC33 to restore it to a known condition.
Figure 23. Timing for SHZ
SM320VC33 SMJ320VC33 test_access_port_timg_SGUS034.gifFigure 24. IEEE-1149.1 Test Access Port Timings