SGUS034F February   2001  – June 2015 SMJ320VC33

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Electrical Characteristics
    4. 6.4  Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements
    5. 6.5  Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements
    6. 6.6  Timing Requirements for EXTCLK, All Modes
    7. 6.7  Timing Requirements for Memory Read/Write for STRB
    8. 6.8  Timing Requirements for XF0 and XF1 when Executing LDFI or LDII
    9. 6.9  Timing Requirements for XF0 and XF1 when Executing SIGI
    10. 6.10 Timing Requirements for Changing XFx from Output to Input Mode
    11. 6.11 Timing Requirements for RESET
    12. 6.12 Timing Requirements for INT3 to INT0 Response
    13. 6.13 Timing Requirements for Serial Port
    14. 6.14 Timing Requirements for HOLD/HOLDA
    15. 6.15 Timing Requirements for Peripheral Pin General-Purpose I/O
    16. 6.16 Timing Requirements for Timer Pin
    17. 6.17 Timing Requirements for IEEE-1149.1 Test Access Port
    18. 6.18 Switching Characteristics for EXTCLK, All Modes
    19. 6.19 Switching Characteristics for Memory Read/Write for STRB
    20. 6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII
    21. 6.21 Switching Characteristics for XF0 when Executing STFI or STII
    22. 6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI
    23. 6.23 Switching Characteristics for Loading when XF is Configured as an Output
    24. 6.24 Switching Characteristics for Changing XFx from Output to Input Mode
    25. 6.25 Switching Characteristics for Changing XFx from an Input to an Output
    26. 6.26 Switching Characteristics for RESET
    27. 6.27 Switching Characteristics for IACK
    28. 6.28 Switching Characteristics for Serial Port
    29. 6.29 Switching Characteristics for HOLD/HOLDA
    30. 6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O
    31. 6.31 Switching Characteristics for Timer Pin
    32. 6.32 Switching Characteristics for SHZ
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  JTAG Scan-Based Emulation Logic
      2. 8.2.2  Clock Generator
      3. 8.2.3  PLL and Clock Oscillator Control
      4. 8.2.4  PLL Isolation
      5. 8.2.5  Clock and PLL Considerations on Initialization
      6. 8.2.6  EDGEMODE
      7. 8.2.7  Reset Operation
      8. 8.2.8  PAGE0 to PAGE3 Select Lines
      9. 8.2.9  Using External Logic With the READY Pin
      10. 8.2.10 Posted Writes
      11. 8.2.11 Data Bus I/O Buffer
      12. 8.2.12 Bootloader Operation
      13. 8.2.13 JTAG Emulation
      14. 8.2.14 Designing a Target System Emulator Connector (14-Pin Header)
      15. 8.2.15 JTAG Emulator Cable Pod Logic
      16. 8.2.16 Reset Timing
      17. 8.2.17 Interrupt Response TIming
      18. 8.2.18 Interrupt-Acknowledge Timing
      19. 8.2.19 Data-Rate Timing Modes
      20. 8.2.20 HOLD Timing
      21. 8.2.21 General-Purpose I/O Timing
      22. 8.2.22 Peripheral Pin I/O Timing
      23. 8.2.23 Timer Pin Timing
    3. 8.3 Register Maps
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing Considerations
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Timing Parameter Symbology
      2. 10.2.2 Device and Development-Support Tool Nomenclature
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFG|164
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

HFG Package
164-Pin CFP
Top View
SM320VC33 SMJ320VC33 po_SGUS034.gif

NOTE:

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.
PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.

GNM Pin Assignments(1)

SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER
A0 J2 D0 G12 DVDD M1 R/W L4
A1 K2 D1 G10 N1 RDY M5
A2 K1 D2 F13 N4 RESET B7
A3 J4 D3 G11 N7 RSV0 B4
A4 H4 D4 H10 M8 RSV1 D5
A5 H3 D5 H13 N12 SHZ D7
A6 H1 D6 H12 L13 STRB M4
A7 G4 D7 J10 H11 TCK F10
A8 G1 D8 J11 F11 TCLK0 C10
A9 G2 D9 J12 B12 TCLK1 A11
A10 F3 D10 K13 A10 TDI E11
A11 F4 D11 K12 A6 TDO D13
A12 F2 D12 K10 A1 TMS E10
A13 E1 D13 M13 DX0 A12 TRST C13
A14 E2 D14 L11 EDGEMODE A7 VSS B1
A15 E4 D15 L12 EMU0 F12 D1
A16 C1 D16 M12 EMU1 E12 G3
A17 C2 D17 L10 EXTCLK C6 J1
A18 D3 D18 K9 FSR0 C12 L2
A19 C3 D19 N11 FSX D10 M3
A20 B2 D20 M11 H1 L3 M6
A21 D4 D21 M10 H3 N2 L7
A22 A2 D22 K8 HOLD N5 N10
A23 B3 D23 N9 HOLDA K5 N13
CLKMD0 C5 D24 M9 IACK K4 K11
CLKMD1 B5 D25 L8 INT0 C8 G13
CLKR0 B13 D26 N8 INT1 B9 E13
CLKX0 B11 D27 M7 INT2 D8 A13
CVDD E3 D28 K7 INT3 A9 C11
J3 D29 L6 MCBL/MP B8 C9
L5 D30 N6 PAGE0 M2 C7
L9 D31 K6 PAGE1 N3 C4
J13 DR0 D11 PAGE2 L1 XF0 B10
D12 DVDD D2 PAGE3 K3 XF1 D9
A8 F1 PLLVDD(2) A5 XIN B6
A3 H2 PLLVSS(2) A4 XOUT D6
(1) DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.
(2) PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.

Pin Functions

PIN TYPE(1) DESCRIPTION CONDITIONS WHEN SIGNAL IS Z TYPE(2)
NAME QTY
PRIMARY-BUS INTERFACE
D31- D0 32 I/O/Z 32-bit data port S H R
Data port bus keepers. (See Figure 30) S
A23- A0 24 O/Z 24-bit address port S H R
R/W 1 O/Z Read/write. R/W is high when a read is performed and low when a write is performed over the parallel interface. S H R
STRB 1 O/Z Strobe. For all external-accesses S H
PAGE0 to PAGE3 1 O/Z Page strobes. Four decoded page strobes for external access S H R
RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction completion.
HOLD 1 I Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 to A0, D31 to D0, STRB, and R/W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until the NOHOLD bit of the primary-bus-control register is set.
HOLDA 1 O/Z Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD. HOLDA indicates that A23 to A0, D31 to D0, STRB, and R/W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set. S
CONTROL SIGNALS
RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector.
EDGEMODE 1 I Edge mode. Enables interrupt edge mode detection.
INT3 to INT0 4 I External interrupts
IACK 1 O/Z Internal acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate when a section of code is being executed. S
MCBL/MP 1 I Microcomputer bootloader/microprocessor mode-select
SHZ 1 I Shutdown high impedance. When active, SHZ places all pins in the high-impedance state. SHZ can be used for board-level testing or to ensure that no dual-drive conditions occur.
CAUTION: A low on SHZ corrupts the device memory and register contents. Reset the device with SHZ high to restore it to a known operating condition.
XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support interlocked processor instruction. S R
SERIAL PORT 0 SIGNALS
CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R
CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R
DR0 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R
DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R
FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive process using DR0. S R
FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit process using DX0. S R
TIMER SIGNALS
TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R
TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S R
SUPPLY AND OSCILLATOR SIGNALS
H1 1 O/Z External H1 clock S
H3 1 O/Z External H3 clock S
CVDD 8 I +VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to a common supply plane.(3)
DVDD 16 I +VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a common supply plane.(3)
VSS 18 I Ground. All grounds must be connected to a common ground plane.
PLLVDD 1 I Internally isolated PLL supply. Connect to CVDD (1.8 V)
PLLVSS 1 I Internally isolated PLL ground. Connect to VSS
EXTCLK 1 I External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is used, tie this pin to ground.
XOUT 1 O Clock out. Output from the internal-crystal oscillator. If a crystal is not used, leave XOUT unconnected.
XIN 1 I Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to ground.
CLKMD0, CLKMD1 2 I Clock mode select pins
RSV0 to RSV1 2 I Reserved. Use individual pullups to DVDD.
JTAG EMULATION
EMU1 to EMU0 2 I/O Emulation pins 0 and 1, use individual pullups to DVDD
TDI 1 I Test data input
TDO 1 O Test data output
TCK 1 I Test clock
TMS 1 I Test mode select
TRST 1 I Test reset
(1) I = input, O = output, Z = high-impedance state
(2) S = SHZ active, H = HOLD active, R = RESET active
(3) Recommended decoupling. Four 0.1 μF for CVDD and eight 0.1 μF for DVDD.