SGUS034F February   2001  – June 2015 SMJ320VC33

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Electrical Characteristics
    4. 6.4  Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing Requirements
    5. 6.5  Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements
    6. 6.6  Timing Requirements for EXTCLK, All Modes
    7. 6.7  Timing Requirements for Memory Read/Write for STRB
    8. 6.8  Timing Requirements for XF0 and XF1 when Executing LDFI or LDII
    9. 6.9  Timing Requirements for XF0 and XF1 when Executing SIGI
    10. 6.10 Timing Requirements for Changing XFx from Output to Input Mode
    11. 6.11 Timing Requirements for RESET
    12. 6.12 Timing Requirements for INT3 to INT0 Response
    13. 6.13 Timing Requirements for Serial Port
    14. 6.14 Timing Requirements for HOLD/HOLDA
    15. 6.15 Timing Requirements for Peripheral Pin General-Purpose I/O
    16. 6.16 Timing Requirements for Timer Pin
    17. 6.17 Timing Requirements for IEEE-1149.1 Test Access Port
    18. 6.18 Switching Characteristics for EXTCLK, All Modes
    19. 6.19 Switching Characteristics for Memory Read/Write for STRB
    20. 6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII
    21. 6.21 Switching Characteristics for XF0 when Executing STFI or STII
    22. 6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI
    23. 6.23 Switching Characteristics for Loading when XF is Configured as an Output
    24. 6.24 Switching Characteristics for Changing XFx from Output to Input Mode
    25. 6.25 Switching Characteristics for Changing XFx from an Input to an Output
    26. 6.26 Switching Characteristics for RESET
    27. 6.27 Switching Characteristics for IACK
    28. 6.28 Switching Characteristics for Serial Port
    29. 6.29 Switching Characteristics for HOLD/HOLDA
    30. 6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O
    31. 6.31 Switching Characteristics for Timer Pin
    32. 6.32 Switching Characteristics for SHZ
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  JTAG Scan-Based Emulation Logic
      2. 8.2.2  Clock Generator
      3. 8.2.3  PLL and Clock Oscillator Control
      4. 8.2.4  PLL Isolation
      5. 8.2.5  Clock and PLL Considerations on Initialization
      6. 8.2.6  EDGEMODE
      7. 8.2.7  Reset Operation
      8. 8.2.8  PAGE0 to PAGE3 Select Lines
      9. 8.2.9  Using External Logic With the READY Pin
      10. 8.2.10 Posted Writes
      11. 8.2.11 Data Bus I/O Buffer
      12. 8.2.12 Bootloader Operation
      13. 8.2.13 JTAG Emulation
      14. 8.2.14 Designing a Target System Emulator Connector (14-Pin Header)
      15. 8.2.15 JTAG Emulator Cable Pod Logic
      16. 8.2.16 Reset Timing
      17. 8.2.17 Interrupt Response TIming
      18. 8.2.18 Interrupt-Acknowledge Timing
      19. 8.2.19 Data-Rate Timing Modes
      20. 8.2.20 HOLD Timing
      21. 8.2.21 General-Purpose I/O Timing
      22. 8.2.22 Peripheral Pin I/O Timing
      23. 8.2.23 Timer Pin Timing
    3. 8.3 Register Maps
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing Considerations
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Timing Parameter Symbology
      2. 10.2.2 Device and Development-Support Tool Nomenclature
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFG|164
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

9.1 Power Sequencing Considerations

Though an internal ESD and CMOS latchup protection diode exists between CVDD and DVDD, it should not be considered a current-carrying device on power up. Use an external Schottky diode to prevent CVDD from exceeding DVDD by more than 0.7 V. The effect of this diode during power up is that if CVDD is powered up first, DVDD follows by one diode drop even when the DVDD supply is not active.

Typical systems using LDOs of the same family type for both DVDD and CVDD track each other during power up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin can be used to asynchronously disable all outputs. RESET should not be used in this case because some signals require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.